Nanosheet FET Gate Stack for Uniform Work Function Thickness
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in maintaining uniformity of work function material thickness, leading to variations in threshold voltage (VTH) and device performance.
Innovation Solution
A method is employed to form a multi-layer stack with alternating semiconductor materials, pattern fins and nanostructures, and use a replacement gate process to create nanosheets, ensuring uniform thickness of work function material by forming a gate layer stack around the nanosheets, comprising interfacial dielectric, gate dielectric, and liner materials to stabilize the work function material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but uniformity of work function material thickness deteriorates leading to threshold voltage variations
Solution Approach 1:
The gate structure is segmented into multiple discrete layers (interfacial dielectric layer, gate dielectric layer, first liner material layer, work function material layer, second liner material layer) that are formed sequentially. This segmentation allows each layer to be independently controlled and optimized, ensuring uniform thickness even as feature sizes are reduced to improve integration density.
Solution Approach 2:
The interfacial dielectric layer and gate dielectric layer are formed preliminarily before the work function material layer. This preliminary action creates a stable foundation and controlled interface that ensures subsequent work function material deposition maintains uniform thickness, preventing threshold voltage variations despite continued scaling.
2Productivity
If device size is reduced to improve integration density, then more components fit in given area, but device performance deteriorates due to threshold voltage variations
Solution Approach 1:
The gate structure is divided into multiple functionally distinct layers, each contributing to device performance. The work function material layer is specifically positioned between liner material layers, creating a segmented structure that isolates and stabilizes the critical work function region, ensuring consistent device performance across scaled dimensions.
Solution Approach 2:
The gate structure employs a composite multi-layer material system combining different dielectric and conductive materials. This composite structure leverages the complementary properties of each material to maintain electrical performance and threshold voltage uniformity, even as the overall device size is reduced for higher integration density.
3Manufacturing precision
If multi-layer gate structure is formed to maintain uniform work function material thickness, then threshold voltage variations are reduced, but device complexity increases
Solution Approach 1:
While segmentation into multiple layers does increase structural complexity, each layer serves a specific, well-defined function. The interfacial dielectric layer provides interface stabilization, the gate dielectric layer provides electrical isolation, the liner material layers provide structural support and adhesion, and the work function material layer provides the critical work function. This functional segmentation makes the complexity manageable and beneficial.
Solution Approach 2:
The invention controls the thickness and material composition parameters of each layer to achieve optimal performance. By carefully adjusting these parameters during fabrication, the multi-layer structure achieves uniform work function material thickness and stable threshold voltage, with the added benefit that parameter optimization can compensate for the increased structural complexity.
Data Source
AI summary
A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.