Nanosheet FET Gate Strapping for Higher Density Without Extra Track Height
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Solution Overview
Problem
Existing semiconductor technologies face challenges in further miniaturizing field-effect transistors (FETs) beyond atomic level scaling, particularly in achieving efficient gate control over nanosheet and nanowire structures.
Innovation Solution
The development of nanosheet FETs with level-to-level gate strapping, involving a stacked configuration of channel layers and a gate structure disposed through these layers, allowing for vertical gate connections and improved gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar FET structures are used, then manufacturing process is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar 2D FET structures to three-dimensional stacked nanosheet FET structures. Multiple channel layers are stacked vertically with gate structures disposed between them, enabling increased device density by utilizing the vertical dimension rather than only lateral scaling.
Solution Approach 2:
The gate structure is nested between the channel layers in a stacked configuration. The gate is disposed between first portions of the channel layers on a first side and second portions on a second side, creating a nested arrangement where the gate is surrounded by channel material on multiple sides, improving gate control while maintaining compact structure.
2Reliability
If gate wrap around structures are implemented, then gate control is improved, but extra track height is required
Solution Approach 1:
Instead of extending the gate laterally in a wrap-around configuration that increases track height, the patent uses vertical stacking of channel layers with the gate disposed between them. This approach achieves superior gate control by surrounding the channel on multiple sides through the stacked arrangement, eliminating the need for extra track height associated with lateral gate wrap-around structures.
3Reliability
If n-type and p-type FET replacement metal gate processes are used, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The stacked nanosheet FET structure with gate disposed between channel layers provides a universal architecture that can be used for both n-type and p-type FETs. This unified structure simplifies the replacement metal gate process by eliminating the need for separate processing steps for different device types, as the same basic structure can accommodate both transistor types through material selection rather than process differentiation.
Data Source
AI summary
A semiconductor device comprises a plurality of channel layers in a stacked configuration, and a gate structure disposed through respective ones of the plurality of channel layers. The gate structure is surrounded on at least three sides by portions of the respective ones of the plurality of channel layers. The gate structure is disposed from an uppermost channel layer of the plurality of channel layers to a lowermost channel layer of the plurality of channel layers.