Nanosheet FET Gate Length Tuning for Leakage and Gate Control
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Solution Overview
Problem
Existing nanosheet field-effect transistors (NS FETs) with fixed gate lengths are not fully satisfactory for optimizing performance across different memory and logic cells, particularly in reducing leakage and improving gate control, as they lack flexibility in tuning gate lengths for various device functions.
Innovation Solution
A method is developed to form semiconductor devices with tunable gate lengths by varying the germanium concentration in SiGe layers and recessing these layers to achieve different gate lengths, allowing for optimized performance in memory cells like SRAM by independently adjusting gate lengths for improved readability and writability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed gate lengths are used in NS FETs, then manufacturing is simplified, but performance optimization for different memory and logic cells is limited
Solution Approach 1:
The patent applies local quality by creating different gate lengths for specific regions or cells within the semiconductor device. By varying the gate length locally in different memory or logic cells, the invention enables optimized performance for each cell type while maintaining a systematic manufacturing approach. This resolves the contradiction by allowing performance optimization flexibility through localized gate length variations without requiring complete redesign of the entire device structure.
Solution Approach 2:
The invention segments the gate structure into multiple regions with different lengths, allowing independent optimization of gate lengths for different functional cells. This segmentation enables the device to achieve adaptability for various memory and logic cell requirements while maintaining manufacturing feasibility through a structured, modular approach to gate formation.
2Reliability
If uniform gate lengths are used across all cells, then manufacturing precision is easier to maintain, but leakage reduction and gate control optimization are compromised
Solution Approach 1:
The patent implements local quality by providing different gate lengths in different regions to optimize reliability metrics such as leakage reduction and gate control. By allowing gate length to vary locally based on functional requirements, the invention achieves improved reliability without requiring complex manufacturing precision control across the entire device, as each region can be optimized independently.
3Adaptability or versatility
If gate lengths are tuned for different cell functions, then device functionality is improved, but manufacturing process complexity increases
Solution Approach 1:
The invention uses segmentation to divide the device into functional units with different gate lengths, enabling improved device functionality for memory and logic cells. The segmented approach allows standard manufacturing processes to be applied to each segment independently, maintaining ease of manufacture while achieving the adaptability needed for different cell functions through the modular segmented structure.
Data Source
AI summary
A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.