Nanosheet FET Source/Drain Ge Gradient for Lower Channel Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for integrated circuit devices with improved performance and reliability, particularly in nanosheet field-effect transistors, to address the increased possibility of process faults during manufacturing and ensure fast operating speed and operational accuracy as integration increases and sizes decrease.
Innovation Solution
The integrated circuit device features a fin-type active region with a channel region and a gate line surrounding it, along with a source/drain region comprising multiple semiconductor layers, where the first semiconductor layer has a high germanium content that decreases towards the boundary with the second semiconductor layer, enhancing carrier mobility and reducing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of integrated circuit devices is reduced and integration increases, then device density and integration capabilities improve, but the possibility of process faults increases and manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The source/drain region is divided into multiple semiconductor layers (first, second, and third semiconductor layers) with different Ge content ratios. This segmentation allows each layer to be optimized independently for specific functions: the first layer provides high carrier mobility near the channel, while the second and third layers provide stress control and structural stability, thereby reducing process faults while maintaining high integration density.
Solution Approach 2:
Different regions of the source/drain structure are assigned different Ge content ratios tailored to local requirements. The first semiconductor layer has high Ge content (10-100 at %) where it contacts the channel to maximize carrier mobility, while the Ge content decreases toward the boundary with the second semiconductor layer. This local optimization improves device performance without compromising manufacturing reliability.
2Reliability
If the Ge content ratio in the first semiconductor layer is increased to improve carrier mobility, then device performance improves, but manufacturing complexity and process control difficulty increase
Solution Approach 1:
The Ge content ratio is varied systematically across different semiconductor layers and positions. The first semiconductor layer contains Ge at 10-100 at % with a gradient decreasing toward the boundary with the second layer. This parameter optimization enhances carrier mobility in the critical region near the channel while managing manufacturing complexity through controlled composition gradients.
Solution Approach 2:
The source/drain region employs a composite structure of multiple semiconductor layers with different Ge content ratios. This composite approach combines the high mobility benefits of Ge-rich materials near the channel with the structural stability of lower Ge content materials in outer layers, achieving improved device reliability without excessive manufacturing complexity.
3Reliability
If a multi-layer semiconductor structure with varying Ge content is used to enhance carrier mobility, then device performance improves, but the number of manufacturing steps and process complexity increase
Solution Approach 1:
The source/drain region is segmented into three semiconductor layers deposited in sequence. This segmentation enables independent optimization of each layer's Ge content for specific functions while following a systematic deposition process that, although multi-step, provides clear process control and repeatability for high device performance.
Solution Approach 2:
The Ge content ratio is changed systematically across layers: the first layer has 10-100 at % Ge decreasing toward its boundary with the second layer, the second layer has controlled Ge content, and the third layer completes the structure. These parameter changes are implemented through controlled deposition processes that balance manufacturing feasibility with enhanced device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the mobility of carriers, decreases channel resistance, and enhances the overall performance and reliability of the nanosheet field-effect transistor, providing stable performance and increased integration capabilities.
Implementation Method 1
a germanium (Ge) content ratio in the first semiconductor layer is greater than or equal to 10 at % and less than 100 at %, and the Ge content ratio in the first semiconductor layer decreases towards a boundary with the second semiconductor layer
Data Source
AI summary
The integrated circuit device includes a fin-type active region extending in a first direction, a channel region on the fin-type active region, a gate line on the channel region and extending in a second direction, and a source/drain region on the fin-type active region and in contact with the channel region, wherein the source/drain region includes a plurality of semiconductor layers including a first semiconductor layer that includes a portion in contact with the channel region and a portion in contact with the fin-type active region, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, a germanium (Ge) content ratio in the first semiconductor layer is greater than or equal to 10 at % and less than 100 at %, and the Ge content ratio in the first semiconductor layer decreases towards a boundary with the second semiconductor layer.