Nanosheet FET Inner Spacer Segmentation for Tight CPP
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Solution Overview
Problem
Nanosheet FET devices face constraints in reducing device spacing and Contacted Gate Poly-Pitch (CPP) due to inner spacer thickness, which limits the packing density of semiconductor devices.
Innovation Solution
The inner spacers are designed as three separate layers - a lower, middle, and upper inner spacer - allowing for thinner deposition and reducing the conformal deposition thickness, enabling closer device spacing without interference and maintaining tall suspension distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the inner spacer thickness is increased to maintain tall suspension distance, then the device spacing must be increased, but this increases the Contacted Gate Poly-Pitch (CPP) and reduces packing density
Solution Approach 1:
The inner spacer is divided into three separate layers (first inner spacer layer, second inner spacer layer, third inner spacer layer) instead of using a single thick layer. This segmentation allows the suspension distance to be maintained through vertical stacking while reducing the lateral footprint and conformal deposition thickness that constrains device spacing.
Solution Approach 2:
The solution transitions from a single-dimensional thick inner spacer to a multi-layered vertical structure. By stacking three thinner inner spacer layers vertically, the patent maintains the required suspension distance (vertical dimension) while reducing the horizontal constraint on device spacing, effectively utilizing the vertical dimension to resolve the horizontal space conflict.
2Area of stationary object
If the conformal deposition thickness is reduced to enable closer device spacing, then the suspension distance decreases, but this compromises device control and performance
Solution Approach 1:
The inner spacer is segmented into three separate deposable layers with intermediate processing steps. Each layer can be deposited conformally with controlled thickness, and the combination of three layers achieves the total suspension distance requirement without requiring a single thick conformal deposition that would constrain device spacing.
Solution Approach 2:
The first inner spacer layer is deposited and processed before the second and third layers. This preliminary action allows each layer to be optimized independently and ensures that the cumulative thickness achieves the required suspension distance while maintaining control over the final device spacing through controlled deposition of each individual layer.
3Area of stationary object
If the device spacing is reduced to increase packing density, then the CPP decreases, but the inner device liner spacers interfere with each other
Solution Approach 1:
By segmenting the inner spacer into three separate layers, the patent reduces the thickness of each individual conformal deposition. This segmentation ensures that even when devices are spaced closely, the thinner individual layers do not overlap or interfere with adjacent devices, while the cumulative thickness maintains the required suspension distance.
Solution Approach 2:
The patent changes the parameter of inner spacer thickness from a single thick layer to multiple thinner layers. This parameter change allows the device spacing to be reduced without causing spacer interference, as each thinner layer can be precisely controlled to fit within the reduced spacing while maintaining the total suspension distance through vertical stacking.
Data Source
AI summary
A nanosheet FET has a substrate, an insulating layer disposed on the substrate, a source disposed on the insulating layer, and a drain disposed on the insulting layer. A plurality of parallel channels electrically and physically connects to and between the source and drain. One or more of the channels is separated from one or more adjacent and parallel channels by a suspension distance with two inner spacers. The inner spacers have three parts: a lower inner spacer, a middle inner spacer, and an upper inner spacer. The inner spacer design enables making the inner spacer using thinner layers of deposited dielectric material. The thinner deposition layers do not close the device spacing as much and enable smaller CPP while maintaining taller suspension distances.