Nanosheet FET Inner Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size to increase integration density, they face challenges such as increased parasitic capacitance and air gaps that affect device performance, which existing technologies have not adequately addressed.
Innovation Solution
The formation of nanosheet field-effect transistors (NSFETs) involves creating dummy inner spacers between nanosheets, replacing them with inner spacers that seal air gaps, and using epitaxial growth for source/drain regions to reduce parasitic capacitance and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then integration density is improved, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
The patent extracts and removes air gaps from between nanosheets and source/drain regions through the inner spacer formation process. By filling these void spaces with dielectric material, the harmful air gaps that cause parasitic capacitance are eliminated, allowing continued scaling while maintaining performance
Solution Approach 2:
The inner spacer acts as an intermediary structure between the nanosheets and source/drain regions. This intermediate element seals the interface, preventing air gap formation and reducing parasitic capacitance while enabling closer integration of components
2Productivity
If feature size is reduced to increase integration density, then integration density is improved, but air gaps are formed that affect device performance
Solution Approach 1:
The patent performs preliminary action by forming the inner spacer structure before final source/drain region formation. This advance preparation prevents air gap formation at the interface, ensuring structural stability and eliminating void spaces that would compromise device reliability
Solution Approach 2:
The patent converts the potentially harmful air gaps into beneficial sealed interfaces. By intentionally forming and then sealing these spaces with inner spacers, the structure that could cause performance degradation is transformed into a controlled feature that improves device stability and eliminates parasitic effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and enhances NSFET performance by sealing air gaps and facilitating epitaxial growth of source/drain regions, leading to improved device efficiency and integration density.
Implementation Method 1
the inner spacers seal air gaps between the inner spacers and the material layer
Implementation Method 2
forming source/drain regions over the fin using epitaxial growth
Data Source
AI summary
A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.