Nanosheet FET Structure With Isolated Channels for Short-Channel Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving further improvements in nanosheet FETs to address the complexity and scaling issues in three-dimensional designs, particularly in ensuring full depletion in the channel region and minimizing short-channel effects.
Innovation Solution
The development of a semiconductor device structure involving a stack of semiconductor layers with alternating first and second semiconductor layers, where the second semiconductor layers form nanosheet channels surrounded by a gate electrode, and the use of selective etching processes to define isolated channels for both PFET and NFET transistors, along with the formation of dielectric and spacer layers to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency increases and costs lower, but processing and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistor designs to three-dimensional nanosheet FET structures where multiple semiconductor layers are stacked vertically. This dimensional change allows increased device density without proportionally increasing manufacturing complexity, as the vertical stacking enables better gate control and fuller depletion of the channel region while maintaining scalable fabrication processes
2Reliability
If three-dimensional nanosheet FET design is implemented to increase device density, then fuller depletion in channel region is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the channel region into multiple discrete nanosheet semiconductor layers stacked vertically, with each sheet surrounded by gate electrode material. This segmentation enables fuller depletion of the channel region by the gate electrode while using selective etching processes to define isolated channels for both PFET and NFET transistors, achieving improved reliability without excessive manufacturing complexity
Solution Approach 2:
The gate electrode material is nested around each nanosheet semiconductor layer in a gate-all-around configuration, with the gate electrode surrounding the channel region on all sides. This nesting structure achieves complete depletion of the channel region while maintaining a scalable manufacturing approach through selective deposition and etching processes
3Reliability
If gate-all-around design is used to minimize short-channel effects, then sub-threshold current swing improves, but device structure complexity increases
Solution Approach 1:
The gate-all-around structure is achieved through vertical stacking of multiple nanosheet channels with gate electrode material wrapping around each channel in three dimensions. This dimensional approach provides superior gate control and steeper sub-threshold current swing compared to planar designs, while the modular stacked architecture keeps structural complexity manageable through systematic fabrication processes
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.