Dual-Layer Isolation in Nanosheet FETs for Gate Overlap Control
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Solution Overview
Problem
The scaling down of integrated circuits increases complexity and gate-drain capacitance due to larger metal gate endcaps and increased source/drain epitaxy size, necessitating improved active area spacing and transistor scaling.
Innovation Solution
A dual-layer isolation structure is formed between adjacent stacks of semiconductor nanostructures, comprising a shell dielectric layer and a core dielectric layer, followed by etching processes to control gate metal overlap with source/drain regions, enhancing wafer yields and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases
Solution Approach 1:
The isolation structure is divided into two distinct layers: a first dielectric layer (shallow trench isolation) and a second dielectric layer (deep trench isolation). This segmentation allows each layer to perform specific functions - the first layer provides basic isolation and planarization, while the second layer provides enhanced isolation and spacing control - thereby managing processing complexity through functional division while maintaining scaling benefits
Solution Approach 2:
The patent introduces a vertical dimension to isolation structures by stacking dielectric layers at different depths. The first dielectric layer is formed at a shallower depth while the second dielectric layer extends to a greater depth, creating a multi-level isolation architecture that provides superior active area spacing without increasing lateral footprint, thus enabling continued scaling
2Power
If metal gate endcap size is increased, then transistor performance is improved, but gate-drain capacitance increases
Solution Approach 1:
The dual-layer dielectric isolation structure acts as an intermediary between the gate metal endcaps and the drain region. By providing enhanced isolation through stacked dielectric layers with different properties (first layer for basic isolation, second layer for enhanced spacing), the structure mediates the interaction between gate endcaps and drain, reducing parasitic capacitance while allowing larger endcap dimensions for improved transistor performance
3Power
If source/drain epitaxy size is increased, then transistor performance is improved, but active area spacing requirements increase
Solution Approach 1:
The patent transitions from single-layer to multi-layer dielectric isolation, utilizing the vertical dimension to provide enhanced active area spacing. The second dielectric layer extends deeper than the first layer, creating additional spacing in the vertical dimension that allows larger source/drain epitaxy structures while maintaining adequate isolation between adjacent transistors in the lateral plane
Data Source
AI summary
A device includes a stack of first semiconductor nanostructures over a substrate and a stack of second semiconductor nanostructures over the substrate. The device includes an isolation structure between the first and second semiconductor nanostructures. The isolation structure includes a core dielectric layer extending from below a top surface of the substrate to a level higher than all of the first and second semiconductor nanostructures. The isolation structure includes a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the semiconductor nanostructures. The spaces between the core dielectric layer and each of the semiconductor nanostructures can be filled with gate dielectric material or with remnants of the shell dielectric layer.