Nanosheet FET Isolation Structure for Tighter Source/Drain Spacing
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Solution Overview
Problem
In advanced semiconductor technology nodes, the increased gate-drain capacitance and larger source/drain epitaxy sizes lead to challenges in scaling down integrated circuit (IC) cell dimensions and maintaining efficient processing, as existing methods struggle to effectively reduce active area spacing and trim source/drain regions without causing electrical bridging or insufficient size issues.
Innovation Solution
The formation of isolation structures between source/drain regions and gate structures, using techniques like double-patterning or multi-patterning processes, allows for the trimming of source/drain regions to a 'forksheet' shape and reduces active area spacing, enabling more compact IC cell dimensions and improved gate-drain capacitance by isolating gate structures and extending through neighboring regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If existing methods are used to reduce active area spacing, then IC cell dimensions can be scaled down, but electrical bridging occurs between source/drain regions
Solution Approach 1:
An isolation structure is introduced as an intermediary element positioned between adjacent source/drain regions. This isolation structure physically separates the source/drain regions, preventing electrical bridging while enabling reduced active area spacing. The isolation structure acts as a mediator that allows the source/drain regions to be closer without direct electrical contact.
Solution Approach 2:
The isolation structure divides the continuous semiconductor region into separate segments by creating distinct boundaries between adjacent source/drain regions. This segmentation approach allows independent control and sizing of each source/drain region while maintaining electrical isolation, enabling tighter packing without bridging.
2Length of moving object
If source/drain regions are trimmed to reduce active area spacing, then IC cell dimensions are reduced, but source/drain regions become insufficiently sized
Solution Approach 1:
The isolation structure creates distinct segmented regions for source/drain areas, allowing each region to be independently sized and controlled. This segmentation enables the source/drain regions to maintain adequate dimensions for manufacturing precision while the isolation structure itself occupies minimal space, thus reducing overall active area spacing.
Solution Approach 2:
The isolation structure provides localized electrical isolation at critical interfaces between source/drain regions, while the source/drain regions themselves maintain their full functional size in non-isolated areas. This local application of isolation allows optimal sizing of source/drain regions without compromising overall spacing.
3Manufacturing precision
If multiple separate processes are used to cut source/drain and gate structures, then precise trimming is achieved, but processing complexity increases
Solution Approach 1:
The isolation structure is designed to serve dual functions: it acts as a mask for cutting source/drain regions and simultaneously serves as an isolation barrier. By merging the masking function and isolation function into a single structure, the need for separate masking and isolation processes is eliminated, reducing processing complexity while maintaining precision.
Solution Approach 2:
The isolation structure performs multiple functions within a single component: electrical isolation between source/drain regions, masking during cutting operations, and potential stress control. This multi-functionality reduces the number of separate process steps needed while achieving the same precision that would otherwise require multiple specialized processes.
Data Source
AI summary
A device includes: a first vertical stack of nanostructures over a substrate; a second vertical stack of nanostructures over the substrate; a first source/drain region abutting the first vertical stack of nanostructures; a second source/drain region abutting the second vertical stack of nanostructures; a first gate structure wrapping around the nanostructures of the first vertical stack; a second gate structure wrapping around the nanostructures of the second vertical stack; a dielectric layer over the first and second source/drain regions; and an isolation structure that extends from an upper surface of the dielectric layer to a level below upper surfaces of the first and second source/drain regions, the isolation structure being between the first source/drain region and the second source/drain region.