Nanosheet FET Multi-Layer Spacers for Low Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in reducing parasitic capacitance and ensuring the structural integrity of components, particularly in nanosheet field-effect transistors (NSFETs), which affect performance and integration density.
Innovation Solution
A method is employed to form a nanosheet field-effect transistor (NSFET) device by creating a multi-layer spacer film within sidewall recesses, using a combination of dielectric materials with different etching selectivities to form sealed air gaps and physically robust inner spacers, reducing parasitic capacitance while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but parasitic capacitance increases and structural integrity deteriorates
Solution Approach 1:
The gate structure is segmented into multiple nanosheets stacked vertically, allowing the gate to wrap around the channel from multiple sides. This segmentation enables better control of parasitic capacitance by distributing the gate control function across multiple separated sheets rather than a single continuous gate, thereby improving integration density while managing parasitic effects
Solution Approach 2:
The patent transitions from a planar 2D gate structure to a 3D vertical stack of nanosheets. By stacking multiple thin gate sheets vertically above the channel, the gate achieves wrap-around control in the vertical dimension, effectively reducing parasitic capacitance at the source-drain junctions while maintaining high integration density
2Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but structural integrity of components deteriorates
Solution Approach 1:
The gate structure employs composite materials with alternating high-k dielectric layers and metal layers. The high-k dielectric provides strong electrical control with thinner physical thickness, while the metal layers provide mechanical strength and conductivity. This composite structure maintains structural integrity at reduced feature sizes while enabling higher integration density
Solution Approach 2:
Multiple nanosheet layers are nested vertically within a compact footprint, with each nanosheet containing a channel, gate, and spacer structure. This nesting approach packs multiple functional units into a small area, achieving high integration density while each nested unit maintains its structural integrity through the self-aligned fabrication process
3Reliability
If multi-layer spacer film is used to reduce parasitic capacitance, then performance improves, but device complexity increases
Solution Approach 1:
The spacer structure uses local quality by applying different dielectric materials at different locations: a first dielectric material forms the inner spacer directly adjacent to the nanosheet for maximum capacitance reduction, while a second dielectric material forms the outer spacer providing mechanical support and stress control. This localized material differentiation optimizes performance while managing structural complexity through functional zonation
Data Source
AI summary
A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.