Nanosheet FET Parasitic Bipolar Effect Suppression
Solution Overview
Problem
Stacked nanosheet FETs are vulnerable to the Parasitic Bipolar Effect (PBE), which leads to increased leakage currents due to the accumulation of minority carriers, making it challenging to maintain low leakage levels required for reliable operation, especially in fully-insulated structures like semiconductor on insulator (xOI) and nanosheet devices.
Innovation Solution
The implementation of a nanosheet FET structure with a doped well and conductive material that provides a conductive path for minority carriers, where the conductive material and well have higher impurity concentrations than the nanosheets, and internal spacers are used to electrically insulate the conductive material from the workfunction metal, reducing PBE gain and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked nanosheet FETs are used to increase effective conduction width in small layout area, then device density and conduction width are improved, but leakage current increases due to Parasitic Bipolar Effect
Solution Approach 1:
A conductive material is introduced as an intermediary component between the nanosheet channel and the substrate. This conductive material provides a dedicated extraction path for minority carriers, preventing their accumulation in the channel region while maintaining the high-density stacked nanosheet structure. The conductive material acts as a mediator that resolves the conflict between high device density and low leakage current.
Solution Approach 2:
The patent applies selective doping to create regions with different impurity concentrations. The conductive material is doped with higher impurity concentration than the nanosheet channel, creating a localized high-conductivity region specifically for minority carrier extraction. This local quality enhancement allows the structure to maintain low leakage without compromising the overall device density.
2Ease of manufacture
If fully-insulated structures like xOI and nanosheet devices are used, then device isolation and integration are improved, but minority carrier accumulation increases leading to higher leakage
Solution Approach 1:
The conductive material serves as an intermediary that reconciles the contradiction between full insulation and carrier extraction. It is embedded within the insulated structure, providing a localized conductive pathway for minority carriers without compromising the overall insulation architecture. This allows fully-insulated structures to maintain their manufacturing advantages while eliminating the leakage problem.
3Reliability
If conductive material is added to suppress PBE, then leakage current is reduced, but device structure complexity increases
Solution Approach 1:
The patent segments the device structure by introducing a distinct conductive material layer separate from the nanosheet channel and substrate. This segmentation allows the minority carrier extraction function to be isolated in a specific region, simplifying the overall design approach. Rather than modifying the entire device structure, the solution is divided into discrete functional components, making the complex PBE suppression task more manageable.
Solution Approach 2:
The patent controls device complexity by adjusting key parameters of the conductive material, such as its impurity concentration, thickness, and lateral dimensions. By optimizing these parameters, the structure achieves effective PBE suppression with minimal added complexity. The conductive material layer is designed with specific parameter ranges that balance leakage suppression performance against structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the PBE gain, allowing for leakage currents of less than 1 nA/μm, enhancing the reliability and performance of nanosheet FETs by providing a conductive path for minority carriers and maintaining electrostatic control.
Implementation Method 1
The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well
Implementation Method 2
The isolation layer may be on the well and may electrically insulate the well from the workfunction metal
Implementation Method 3
The well may be doped with impurities. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of a same conductivity type as the impurities of the well
Data Source
AI summary
A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal.