Nanosheet FET Substrate Isolation via Rare Earth Oxide Layers
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Solution Overview
Problem
Fabricating nanosheet FET devices poses a challenge in effectively isolating them from the underlying semiconductor substrate, leading to unwanted current leakage and parasitic capacitance due to the formation of parasitic transistor channels.
Innovation Solution
The use of rare earth oxide (REO) layers as substrate isolation layers, which are formed on the semiconductor substrate and between the semiconductor channel layers, to prevent junction leakage and parasitic capacitance by electrically isolating the metal gate structure and source/drain regions from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the semiconductor substrate below the parasitic transistor channel is heavily doped to suppress leakage current, then leakage current is reduced, but junction leakage between source/drain regions and the heavily doped semiconductor substrate increases and parasitic capacitance between the gate and the heavily doped semiconductor substrate increases
Solution Approach 1:
An insulating layer is introduced as an intermediary between the metal gate structure and the semiconductor substrate. This insulating layer includes a first portion between the metal gate structure and the source/drain regions, and a second portion between the metal gate structure and the semiconductor substrate. The insulating layer mediates the interaction between the gate and substrate, preventing direct contact that would cause parasitic effects while maintaining electrical isolation.
Solution Approach 2:
The insulating layer is segmented into distinct portions with different functions: a first portion providing isolation from source/drain regions and a second portion providing isolation from the semiconductor substrate. This segmentation allows optimized isolation at each interface without compromising the other, resolving the contradiction between suppressing substrate leakage and preventing junction leakage.
2Device complexity
If a nanosheet FET device is formed without substrate isolation, then device structure is simpler, but parasitic transistor channels form in the semiconductor substrate causing unwanted current leakage and parasitic capacitance
Solution Approach 1:
An insulating layer is introduced as an intermediary between the metal gate structure and the semiconductor substrate. This insulating layer mediates the interaction between the gate and substrate, preventing direct contact that would cause parasitic effects while maintaining electrical isolation.
Solution Approach 2:
The isolation approach moves from lateral isolation (in the plane of the substrate) to vertical isolation (through the insulating layer thickness). By adding the insulating layer in the vertical dimension, the patent achieves effective isolation without increasing lateral device footprint or complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The REO layers effectively suppress junction leakage and parasitic capacitance, enhancing the performance of nanosheet FET devices by improving isolation and reducing unwanted current flow.
Implementation Method 1
the REO layer isolates the metal gate structure from the semiconductor substrate
Data Source
AI summary
Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.