Nanosheet FET Source/Drain Layout to Prevent Short Circuits
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Solution Overview
Problem
The challenge in developing integrated circuit devices is to optimize the structure of transistors for high operating speed and accuracy, particularly in achieving efficient source/drain regions and epitaxial structures that enhance performance while preventing short circuits and process variations.
Innovation Solution
The integrated circuit device incorporates a rear wiring structure, insulating substrate with fin structures, device isolation layers, gate structures, nanosheet stacks, and semiconductor epitaxial structures, with specific source/drain regions and contacts designed to optimize channel regions and prevent short circuits through precise layering and epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional transistor structures are used for down-scaling, then device size is reduced, but operating speed and accuracy deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet stacks with gate-all-around configuration. The channel region is formed as multiple stacked nanosheets (first, second, and third nanosheets) surrounded by gates on all sides, enabling efficient carrier transport in vertical and horizontal directions simultaneously, thus maintaining high operating speed while achieving device down-scaling
Solution Approach 2:
The gate structures are positioned to surround the nanosheet stacks on all sides, with gates nested around the channel region in a gate-all-around configuration. This nested arrangement provides maximum gate control over the channel while minimizing device footprint, resolving the contradiction between size reduction and performance maintenance
2Measurement precision
If advanced epitaxial structures are introduced to enhance performance, then operating accuracy is improved, but device complexity increases
Solution Approach 1:
The channel region is segmented into multiple discrete nanosheets stacked vertically, with each nanosheet providing an independent conduction path. This segmentation increases the effective channel area and improves carrier transport efficiency, enhancing operating accuracy while the modular nature of stacked nanosheets keeps the fabrication process manageable
Solution Approach 2:
The device employs composite material structures including semiconductor-sacrificial semiconductor composites for nanosheet formation, and multiple layers of insulating materials with different properties (first and second insulating layers, third insulating layer) to achieve precise electrical characteristics and control device behavior
3Speed
If source/drain regions are optimized for high performance, then operating speed is improved, but short circuit risk increases
Solution Approach 1:
A sacrificial semiconductor layer is introduced as an intermediary structure during fabrication. This layer is positioned between the source and drain regions and is selectively removed to form the nanosheet channel, preventing direct contact between source and drain that would cause short circuits, while still enabling high-performance carrier transport through the engineered nanosheet structure
Solution Approach 2:
The sacrificial semiconductor layer is extracted from the final device structure after serving its purpose in defining the channel region. By removing this intermediary layer, clean source/drain contacts are formed while the nanosheet channel maintains proper electrical isolation, preventing short circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of integrated circuit devices by improving source/drain regions and epitaxial structures, ensuring high operating speed and accuracy while minimizing short circuits and process variations, thus addressing the demand for advanced transistor design.
Implementation Method 1
a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region
Data Source
AI summary
An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.