Nanosheet FET Spacer Layout for Lower Source/Drain Resistance
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Solution Overview
Problem
As minimum feature size reduces in semiconductor devices, the resistance of source/drain features increases, affecting device performance.
Innovation Solution
The integration of nanosheet channel FETs with specific spacer and epitaxial structure configurations, including wider isolation structures and varying spacer widths, to reduce capacitance and enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but source/drain resistance increases and device performance deteriorates
Solution Approach 1:
The patent implements different spacer widths at different locations: wider spacers are formed at source/drain regions to reduce resistance, while narrower spacers are used in other regions to maintain integration density. This local differentiation allows optimization of electrical properties without sacrificing overall device integration.
Solution Approach 2:
The patent transitions from planar device structures to three-dimensional nanosheet channel structures with vertical stacking. By utilizing the vertical dimension, the patent achieves higher integration density while maintaining adequate source/drain dimensions for acceptable resistance levels through the epitaxial growth process.
2Area of stationary object
If feature dimensions are reduced to improve integration density, then chip area utilization increases, but source/drain resistance increases
Solution Approach 1:
The patent applies selective spacer width design where wider spacers are specifically positioned at source/drain contact regions to maintain lower resistance, while other regions use narrower spacers to maximize area utilization. This localized approach allows precise control of electrical properties independent of overall device scaling.
Solution Approach 2:
The patent changes the spacer width parameter spatially across the device structure. By varying the spacer width from narrow in most regions to wide at source/drain regions, the patent independently controls resistance characteristics without being constrained by uniform scaling rules, thereby maintaining manufacturing precision for resistance control.
Data Source
AI summary
An integrated circuit includes a first transistor and a second transistor. A first gate spacer is along a first portion of the common gate structure, the first gate spacer having a first width. A first inner spacer is between the first semiconductor channel layers and having a second width, the first width being greater than the second width. A second gate spacer is along a second portion of the common gate structure and having a third width. A second inner spacer is between the second semiconductor channel layers and having a fourth width, and the third width is greater than the fourth width, and the second width is greater than the fourth width. An isolation structure is in contact with one end of the common gate structure, the isolation structure having a fifth width, and the fifth width is greater than the first width and the third width.