Nanosheet FET Spacer Structure for Source/Drain Width Control
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Solution Overview
Problem
As IC devices become more downscaled, they require high operating speed and accuracy, but the increased integration density and smaller size lead to higher possibilities of process defects during manufacturing of nanosheet FETs, necessitating a new structure that enhances performance and reliability.
Innovation Solution
The IC device incorporates a fin-type active region with gate lines and insulating spacer structures, including a silicon oxycarbide (SiOC) film doped with 0 to 5% nitrogen atoms, to cover the gate lines and source/drain regions, providing stable performance and increased reliability by preventing process defects and controlling lateral growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC devices are downscaled to increase integration density, then operating speed and accuracy are improved, but process defects increase during manufacturing
Solution Approach 1:
The spacer structure is divided into three distinct portions: a first spacer portion covering the gate line sidewall, a second spacer portion covering the source/drain region sidewall, and a spacer corner portion filling the corner space. This segmentation allows each portion to be optimized for its specific function, preventing process defects while maintaining high integration density.
Solution Approach 2:
Different regions of the spacer structure are provided with different properties through the three portions. The first spacer portion has properties optimized for gate line coverage, the second spacer portion for source/drain region coverage, and the spacer corner portion for corner space filling. This local quality differentiation ensures reliable performance in each specific area.
2Area of stationary object
If the size of IC devices is decreased to increase integration density, then more devices fit on the chip, but the possibility of process defects increases
Solution Approach 1:
The insulating spacer structure is formed in advance to define precise boundaries for the source/drain regions before manufacturing processes proceed. The three portions (first spacer portion, second spacer portion, and spacer corner portion) are preliminarily positioned to prevent lateral growth and ensure accurate dimensional control, thereby reducing process defects even as device size decreases.
3Manufacturing precision
If insulating spacer structures are used to control lateral growth of source/drain regions, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The three separate spacer portions (first spacer portion, second spacer portion, and spacer corner portion) are integrally connected to form a unified insulating spacer structure. This merging approach maintains the functional benefits of differentiated regions while simplifying the overall structure compared to completely separate components, thereby controlling lateral growth without excessive complexity.
Data Source
AI summary
An integrated circuit device includes a gate line disposed on a fin-type active region, a source/drain region disposed on the fin-type active region, and an insulating spacer structure that covers the gate line and the source/drain region. The insulating spacer structure includes a first spacer portion that covers the sidewall of the gate line, a second spacer portion integrally connected to the first spacer portion, where the second spacer portion protrudes in a first lateral direction and covers a partial region of a sidewall of the source/drain region, and a spacer corner portion that fills a corner space defined by the gate line and the source/drain region between the first spacer portion and the second spacer portion. The insulating spacer structure has a single film structure that includes a SiOC film doped with about 0 at % to about 5 at % of nitrogen atoms.