Nanosheet FET Structure With Stacked Source-Drain for Dense SRAM
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving higher device density and performance while managing the complexity of three-dimensional designs, such as multi-gate field effect transistors, where further improvements in nanostructure FETs are needed to address scaling down transistor dimensions.
Innovation Solution
A semiconductor device structure is developed with a stack of semiconductor layers comprising alternating SiGe and Si layers, forming nanosheet channels surrounded by a gate electrode layer, utilizing epitaxial growth processes and advanced patterning techniques to create isolated channels for both PFET and NFET transistors, enhancing device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor dimensions are scaled down to increase device density, then functional density increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistor designs to three-dimensional vertically stacked nanosheet FETs. Multiple semiconductor layers are stacked vertically to form multiple channels, increasing device density by utilizing the vertical dimension rather than simply scaling down horizontal dimensions. This dimensional transition allows higher functional density while managing manufacturing complexity through standardized vertical stacking processes.
Solution Approach 2:
The semiconductor structure is divided into multiple discrete layers including alternating SiGe and Si layers, with each layer serving specific functions. The stack is segmented into individual nanosheets that form separate channels, allowing independent control and optimization of each transistor channel while maintaining compact vertical integration.
2Quantity of substance
If three-dimensional multi-gate FET structures are implemented to increase device density, then functional density improves, but processing complexity increases
Solution Approach 1:
sacrificial layers are formed beforehand between the semiconductor layers during the stacking process. These preliminary sacrificial structures enable subsequent selective removal to create suspended nanosheet channels with gate-all-around configuration. The preliminary formation of these layers simplifies the overall processing by establishing a template for the final three-dimensional structure.
Solution Approach 2:
Sacrificial layers act as intermediary structures during fabrication. These temporary layers are formed between semiconductor layers to enable precise positioning and separation of nanosheets. The sacrificial material serves as a mediator that facilitates the creation of complex three-dimensional gate structures, which are then removed to leave the desired channel configurations.
3Area of stationary object
If vertically stacked source and drain regions are formed to reduce area requirements, then area efficiency improves, but fabrication complexity increases
Solution Approach 1:
Source and drain regions are merged vertically into stacked configurations where multiple source/drain pairs are integrated along the vertical axis. This combining of multiple regions in the vertical dimension reduces the horizontal footprint while maintaining all necessary electrical connections through standardized contact formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure increases device density and reduces area requirements, enabling efficient fabrication of SRAMs with vertically stacked source and drain regions, improving manufacturing efficiency and lowering costs.
Implementation Method 1
utilizing epitaxial growth processes and advanced patterning techniques to create isolated channels
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain region, a second source/drain region adjacent the first source/drain region, an interlayer dielectric layer disposed between the first source/drain region and the second source/drain region, and a conductive feature disposed in the interlayer dielectric layer between the first source/drain region and the second source/drain region. The conductive feature includes a first portion and a second portion extending from the first portion, and an angle is formed between the first portion and the second portion. The angle is less than about 180 degrees. The conductive feature is electrically connected to the first source/drain region.