Nanosheet FET Strain Tuning via Spacer Recess
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving varied strain in nanoscale field effect transistor (FET) devices, which affects their performance due to material and process variations during fabrication, particularly in multi-gate structures and CMOS circuits.
Innovation Solution
The method involves forming semiconductor devices with horizontal nanosheet stacks for n-channel and p-channel components, using sacrificial layers of SiGe and Si materials with varying Ge content and internal spacer recess lengths to induce tensile or compressive strain, allowing for distinct strain configurations in nMOS and pMOS components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform strain is applied to all channel layers in multi-gate FET structures, then fabrication process simplicity is maintained, but device performance is limited due to inability to optimize for different channel materials and device configurations
Solution Approach 1:
The patent implements local quality by applying different strain configurations to different channel layers within the same multi-gate FET structure. Specifically, first channel layers (e.g., n-type) are configured with first strain (tensile strain) while second channel layers (e.g., p-type) are configured with second strain (compressive strain), allowing each layer to be optimized for its specific device type and material characteristics, thereby improving overall device performance without requiring complete structural redesign
Solution Approach 2:
The patent segments the strain configuration into distinct components: first channel layers receive first strain through first sacrificial layers with first removal depth, while second channel layers receive second strain through second sacrificial layers with second removal depth. This segmentation allows independent optimization of strain parameters for different channel materials and device configurations, resolving the contradiction between performance optimization and process simplicity
2Productivity
If varied strain configurations are implemented for different channel layers, then device performance is optimized, but fabrication process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers with predetermined removal depths before final device assembly. First sacrificial layers are formed with first removal depth and second sacrificial layers with second removal depth, allowing varied strain to be pre-configured in different channel layers. This preliminary stratification enables subsequent simplified processing while achieving optimized strain distribution, thereby improving device efficiency without proportionally increasing fabrication complexity
Solution Approach 2:
The patent utilizes parameter changes by varying the removal depth parameter of sacrificial layers to control strain magnitude and type in different channel layers. By adjusting the removal depth (first removal depth vs. second removal depth), the patent optimizes strain parameters for different channel materials and device configurations, achieving improved device efficiency through controlled parameter variation rather than fundamental process changes
3Reliability
If strain is introduced during fabrication, then channel performance is enhanced, but manufacturing precision requirements increase due to material and process variations
Solution Approach 1:
The patent introduces sacrificial layers as intermediary structures that mediate strain introduction to channel layers. These sacrificial layers are formed with controlled removal depths (first removal depth, second removal depth) to indirectly induce desired strain in channel layers without requiring direct strain application. This intermediary approach buffers against material and process variations, maintaining manufacturing precision while achieving enhanced channel performance through controlled strain
Solution Approach 2:
The patent implements feedback control by measuring and adjusting sacrificial layer removal depth to achieve target strain parameters in channel layers. Through iterative process control and measurement of removal depth, the patent compensates for material and process variations, ensuring consistent strain-induced channel performance while maintaining manufacturing precision. The feedback loop connects removal depth measurement to strain outcome, enabling precise control despite variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the tuning of strain in nMOS and pMOS components, enhancing the performance of nanoscale FET devices by optimizing channel strain parameters, thereby improving the scalability and efficiency of CMOS circuits.
Implementation Method 1
strain may be introduced in the channel or channels of the devices. The strain may be a physical or mechanical result of the materials and process sequences used in fabricating the structure
Data Source
AI summary
A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.