Nanosheet FET Gate Trench Isolation for Backside TSV Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication processes on the backside of semiconductor substrates, particularly for forming conductive patterns through through-silicon-via (TSV) connections, face larger process windows compared to those on the frontside, complicating the manufacturing of semiconductor devices as they become smaller.
Innovation Solution
A method is developed that involves manufacturing semiconductor devices by performing processes on both the frontside and backside of the substrate, including forming fin structures, embedding them in insulating layers, creating sacrificial gate structures, and etching to define source/drain regions, followed by flipping the substrate for further backside processing to form conductive connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fabrication processes are performed on the backside of the substrate for TSV connections, then process window is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct frontside and backside processing stages. The backside process includes separate steps for forming conductive patterns, opening trenches, filling with conductive material, and planarization. This segmentation allows each stage to be optimized independently, improving the overall process window while managing complexity through systematic organization.
Solution Approach 2:
Conductive patterns are formed on the backside of the substrate before the substrate is flipped for frontside processing. This preliminary action enables TSV connections to be established early in the manufacturing sequence, improving process window by allowing subsequent frontside processes to proceed with better control and alignment.
2Ease of manufacture
If substrate is flipped for backside processing, then conductive pattern integration is improved, but process sequence complexity increases
Solution Approach 1:
Instead of forming all conductive patterns on the frontside before flipping, the methodology inverts the sequence by forming conductive patterns on the backside first. This inversion simplifies the integration of TSV connections by establishing them before frontside processing, reducing the overall process sequence complexity despite the additional flip operation.
3Manufacturing precision
If fin structures are embedded in insulating layers, then pattern fidelity is improved, but manufacturing steps increase
Solution Approach 1:
Fin structures are embedded within insulating layers, creating a nested configuration where the fin structures are contained within the insulating material. This nesting approach improves pattern fidelity by providing mechanical support and electrical isolation, while the insulating layer serves multiple functions including planarization and protection, thereby reducing the net increase in manufacturing steps.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a FET structure is formed over a substrate, which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, a gate electrode disposed over the gate dielectric layer and a source/drain structure. A gate cap conductive layer is formed over the gate electrode, the bottom fin structure is replaced with a dielectric fin structure, spacers are formed on opposite sides of the dielectric fin structure, a trench is formed by etching the gate electrode using the dielectric fin and the spacers as an etching mask until the gate cap conductive layer is exposed, and the trench is filled with a first dielectric material.