Nanosheet FET Source/Drain Asymmetry for Scaled ICs
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Solution Overview
Problem
Existing IC devices face challenges in maintaining desired electrical properties when device regions are downscaled, particularly in ensuring optimal performance and reliability of transistors with varying configurations and arrangements on a substrate.
Innovation Solution
The IC device incorporates fin-type active regions with nanosheet stacks and controlled source/drain regions, where the width and positioning of source/drain regions are tailored to enhance electrical properties, including gate structures that surround nanosheet stacks and vary in lateral directions to optimize transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the area of device region is reduced through downscaling of IC devices, then higher integration density is achieved, but maintaining desired electrical properties and optimal transistor performance becomes difficult
Solution Approach 1:
The patent applies local quality by creating asymmetric source/drain regions with different widths on opposite sides of the nanosheet stack. The first source/drain region has a first width while the second source/drain region has a second width greater than the first width, allowing each region to be optimized for its specific function - one for stress application and the other for current flow - thereby maintaining electrical performance in downscaled devices
Solution Approach 2:
The patent directly implements asymmetry by intentionally designing the second source/drain region to have a greater width than the first source/drain region. This asymmetric configuration allows different electrical properties to be achieved on opposite sides of the transistor, with the wider region providing enhanced stress application to improve carrier mobility while the narrower region maintains proper current flow characteristics
2Adaptability or versatility
If different electrical properties are desired for different device types on the same substrate, then device versatility is improved, but maintaining optimal performance for each device type becomes challenging
Solution Approach 1:
The asymmetric source/drain configuration enables different electrical properties to be achieved for different device types (e.g., NMOS and PMOS) on the same substrate. By controlling the width ratio between the first and second source/drain regions, each transistor type can be optimized for its specific electrical characteristics while maintaining reliable performance
Solution Approach 2:
The patent utilizes parameter changes by varying the width of the second source/drain region relative to the first source/drain region. This width parameter adjustment allows optimization of stress application and current flow characteristics for different device types, enabling versatile electrical properties while maintaining optimal performance for each transistor type
Data Source
AI summary
An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source/drain region in contact with one sidewall of the first nanosheet stack, and a second source/drain region in contact with another sidewall of the first nanosheet stack, wherein a greatest width of the first source/drain region is less than a greatest width of the second source/drain region in the second lateral direction may be provided.