Stacked Nanosheet GAA FET Structure for Short-Channel Control
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Solution Overview
Problem
As semiconductor technology advances to sub-10-15 nm nodes, gate-all-around (GAA) FETs require further improvements to address the challenge of full depletion in the channel region and reduce short-channel effects.
Innovation Solution
A GAA FET design with vertically stacked multiple channels in the form of nanosheets or nanowires, surrounded by a gate dielectric and electrode layer, incorporating specific materials and structures to enhance control and performance, including buffer layers, gate dielectric materials, and epitaxial source/drain layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Fin FET gate structure is used, then fabrication complexity is reduced, but gate control over channel is insufficient leading to short-channel effects
Solution Approach 1:
The patent transitions from planar Fin FET gate structure to three-dimensional GAA FET where the gate electrode completely surrounds the channel region in the vertical dimension. This wrap-around gate structure provides superior electrostatic control over the channel, effectively suppressing short-channel effects while maintaining fabrication feasibility through sequential layer formation processes.
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm, then device density and performance are improved, but short-channel effects increase and full depletion becomes difficult to achieve
Solution Approach 1:
The GAA FET structure extends gate control into the vertical dimension with the gate electrode wrapping around the channel on all sides. This three-dimensional configuration provides enhanced electrostatic control that enables full depletion of the channel region even at sub-10-15 nm scale, effectively suppressing short-channel effects while maintaining high device density.
Solution Approach 2:
The gate electrode is positioned to completely surround the channel region, with the gate dielectric layer nested between them. This nested configuration ensures that the gate electric field penetrates the entire channel cross-section, achieving full depletion and suppressing short-channel effects at scaled dimensions.
3Reliability
If GAA FET with wrap-around gate is used, then full depletion and short-channel effect reduction are achieved, but device complexity increases
Solution Approach 1:
The GAA FET structure is divided into distinct sequential layers: channel-forming layers, gate dielectric layer, and gate electrode layer. Each layer is formed independently through separate deposition and patterning steps, which simplifies the overall manufacturing process despite the three-dimensional final structure, making the complex GAA architecture more controllable and manufacturable.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.