Nanosheet GAA I/O Oxide Integration Without Extra Die Area
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Solution Overview
Problem
The integration of thick oxide layers in nanosheet gate-all-around devices for input/output (I/O) devices is challenging due to limited space, leading to performance degradation and increased die area, as existing solutions like cascoding or stacking thin oxide core devices increase cost and decrease performance.
Innovation Solution
A method for integrating nanosheet core transistors with I/O transistors by forming thicker gate oxides using selective oxygen implantation and annealing or atomic layer deposition, allowing for uniform gate-all-around metal electrode layers in a single nanosheet process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick oxide is integrated in nanosheet gate-all-around devices for I/O devices, then I/O voltage handling capability is improved, but available space for gate-all-around metal electrode layers is reduced
Solution Approach 1:
The patent transitions from planar FET to three-dimensional nanosheet gate-all-around architecture, utilizing vertical stacking to increase functional density. By wrapping the gate electrode around the nanosheet channel in a gate-all-around configuration, the design achieves superior electrostatic control while maintaining compact footprint, thereby accommodating thicker oxide layers without proportionally increasing device area.
Solution Approach 2:
The gate electrode structure is designed to completely surround the nanosheet channel, with the oxide layer nested between them. This nested configuration allows the thick oxide to be integrated within the vertical stack rather than occupying lateral space, enabling I/O voltage handling while preserving area for metal electrode layers.
2Reliability
If thick oxide is used in I/O devices, then voltage handling is improved, but the number of stacked nanosheet layers must be reduced compared to core devices
Solution Approach 1:
The patent implements different oxide thicknesses in different device regions on the same die. I/O devices receive thick oxide for voltage handling, while core devices receive thin oxide for high-performance switching. This local differentiation allows each device type to be optimized independently, maintaining full stack heights in both regions without compromise.
Solution Approach 2:
The oxide thickness parameter is varied across different device regions through selective processing steps. By controlling oxidation conditions locally, the patent achieves thick oxide in I/O regions and thin oxide in core regions, enabling both voltage handling and high-performance switching without reducing the number of stacked nanosheet layers in either device type.
3Reliability
If thick oxide is integrated in nanosheet devices, then I/O device performance is improved, but non-uniform or curved silicon nanosheet channels are required which undercut the inner spacers
Solution Approach 1:
The patent forms the nanosheet stack and inner spacers before integrating the thick oxide. This preliminary structuring establishes precise geometric references that guide subsequent oxide formation, ensuring uniform oxide thickness and preventing the need for curved or non-uniform nanosheet channels. The pre-formed spacers act as templates that maintain manufacturing precision throughout the process.
Solution Approach 2:
The patent separates the formation of the nanosheet channel structure from the oxide integration process. By first creating uniform nanosheets with precise dimensions and then selectively adding thick oxide through controlled oxidation, the method maintains nanosheet uniformity while achieving the required oxide thickness for I/O performance, avoiding the need for undercutting or curved channels.
4Reliability
If cascoding or stacking thin oxide core devices is used to support I/O voltages, then I/O voltage handling is achieved, but die area increases and cost increases while performance decreases
Solution Approach 1:
The patent creates a universal nanosheet fabrication platform that can produce both I/O devices with thick oxide and core devices with thin oxide using the same process flow. This multi-functional approach eliminates the need for separate device architectures or additional processing steps, achieving voltage handling in I/O devices without increasing die area or cost, while maintaining high performance in both device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of core and I/O nanosheet transistors with thicker gate oxides on the same die, maintaining performance and design efficiency while minimizing additional processing steps.
Implementation Method 1
each silicon nanosheet located over an I/O region is selectively implanted with deep and shallow oxygen implants
Implementation Method 2
After annealing the Si/SiGe superlattice structure, the oxygen implants are restructured with an oxide self-assembly effect to form oxide layers
Implementation Method 3
an initial set of fabrication steps form a Si/SiGe superlattice structure for I/O nanosheet stack transistors on a wafer substrate by sequentially depositing atomic layer deposition (ALD) oxide, electron-enhanced ALD silicon, and electron-enhanced ALD silicon germanium
Data Source
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AI summary
A semiconductor device and fabrication method are described for integrating I/O and core nanosheet transistors in a single nanosheet process flow by processing a stack of alternating first and second semiconductor structures formed on a substrate, where the first semiconductor structures located over a I/O thick oxide transistor region include a planar semiconductor channel layer sandwiched between upper and lower dielectric layers, and where the alternating first and second semiconductor structures are processed to form gate-all-around electrodes in a core transistor stack that are connected over a relatively thinner gate dielectric layer to control one or more first planar semiconductor channel layers in the core transistor stack, and to form gate-all-around electrodes in an I/O transistor stack that are connected over a relatively thicker gate dielectric layer to control one or more second planar semiconductor channel layers in the I/O transistor stack.