Wrapped Nanosheet Gate Structure With Backside Etch-Back
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in reducing the coupling capacitance between the extruded gate structure and adjacent source/drain contact features due to unwanted Shallow Trench Isolation (STI) oxide loss, which complicates the processing and manufacturing of advanced semiconductor devices.
Innovation Solution
A back-side gate etch back process is employed to etch away excess material of the gate structure, thereby reducing the coupling capacitance, and the formation of nanosheet channel FETs is facilitated through methods like double-patterning or multi-patterning processes, using photolithography and self-aligned techniques to create patterns with smaller pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a gate structure is formed to wrap around nanostructures and extend between stacks, then device complexity and functionality are improved, but coupling capacitance between the gate structure and adjacent source/drain contact features increases due to unwanted STI oxide loss
Solution Approach 1:
The patent extracts and removes the unwanted STI oxide material from between the gate structure and source/drain contact features through selective etching processes. This extraction eliminates the harmful coupling capacitance while preserving the desired gate structure complexity and functionality.
Solution Approach 2:
The patent applies local quality by creating different oxide thicknesses or compositions in different regions. Specifically, the STI oxide is selectively removed or modified in the region between the gate and source/drain contacts to reduce coupling capacitance, while maintaining the gate structure's wrapping configuration elsewhere.
2Manufacturing precision
If photolithography and self-aligned techniques are used to create patterns with smaller pitches, then manufacturing precision is improved, but processing complexity increases
Solution Approach 1:
The patent employs preliminary action through self-aligned techniques where masks and patterns are pre-positioned relative to existing structures. This preliminary alignment reduces the need for complex post-processing steps and achieves small pitch precision while managing processing complexity.
Solution Approach 2:
The patent uses intermediary elements such as sacrificial masks and alignment layers that facilitate the creation of small pitch patterns. These intermediaries enable precise pattern formation through photolithography while simplifying the overall processing sequence by providing reference structures for alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces coupling capacitance and enhances the manufacturing efficiency of semiconductor devices by improving the precision and complexity of gate structures, allowing for more complex and smaller circuit designs.
Implementation Method 1
A back-side gate etch back process is employed to etch away excess material of the gate structure
Implementation Method 2
using photolithography and self-aligned techniques to create patterns with smaller pitches
Data Source
AI summary
A method of manufacturing a semiconductor device is described. The method includes at least the following steps. A substrate is patterned, to form fins physically connected by the substrate. Stacks are formed over the fins respectively, and each stack includes nanostructures stacked over one another. Isolation regions are formed in the substrate between the stacks. A gate structure is formed, to wrap around the nanostructures of the stacks and extend between the stacks. The substrate is turned over. After turning over the substrate, portions of the isolation regions and the substrate are removed, to physically separate the fins from each other.