Nanosheet Gate Stack Layout With Blocking Walls for Leakage Control
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Solution Overview
Problem
As semiconductor technology advances, the scaling down of integrated circuits (ICs) leads to challenges such as increased complexity and reduced geometry sizes, which pose difficulties in maintaining efficient production and cost-effectiveness, particularly in forming gate stacks for advanced transistors like FinFETs and GAA devices.
Innovation Solution
A method for forming gate stacks in semiconductor devices involves alternating layers of SiGe and Si, using photolithography and self-aligned processes to create patterned semiconductor strips, spacers, and strained layers, with blocking walls and inner spacers to define channel regions and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost-effectiveness are improved, but manufacturing precision and process control become more difficult
Solution Approach 1:
The patent segments the gate stack formation into multiple distinct stages: forming semiconductor strips with alternating Si/SiGe layers, creating spacers, forming blocking walls, and selectively removing portions. This segmentation allows each step to be optimized independently, maintaining precision even as overall geometry scales down
Solution Approach 2:
The patent performs preliminary actions by pre-forming the alternating Si/SiGe semiconductor strips and spacers before final gate stack completion. The blocking walls are also formed in advance to define channel regions, enabling better control during subsequent processing steps at reduced geometries
2Reliability
If alternating SiGe and Si layers are used to form semiconductor strips, then strain on channel regions is improved and device performance is enhanced, but process complexity increases
Solution Approach 1:
The patent applies local quality by creating alternating SiGe and Si layers where SiGe provides strain for enhanced carrier mobility in specific channel regions, while Si regions provide relaxation. This localized material differentiation optimizes device performance without requiring complex processing throughout the entire structure
Solution Approach 2:
The spacers formed between semiconductor strips act as intermediaries that define and isolate channel regions. These spacers enable the alternating Si/SiGe structure to be formed with controlled precision, managing the complexity of creating multiple material layers while maintaining device performance benefits
3Manufacturing precision
If blocking walls and inner spacers are formed to define channel regions, then control over transistor operations is improved, but manufacturing steps and device complexity increase
Solution Approach 1:
The patent segments the channel definition into blocking walls and inner spacers, with each element serving a specific function. Blocking walls define outer boundaries while inner spacers create internal channel regions, allowing precise control of transistor operations through structured segmentation rather than monolithic design
Solution Approach 2:
The patent implements nesting by placing inner spacers within the structure defined by blocking walls. This nested arrangement allows multiple levels of channel region definition, achieving precise control over transistor operations while organizing complexity in a hierarchical manner that simplifies fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient gate stacks that enhance device performance by reducing leakage and improving strain on channel regions, leading to better control over transistor operations and increased production efficiency.
Implementation Method 1
epitaxially growing strained layers from the recesses
Data Source
AI summary
A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and a blocking wall. The substrate includes first and second fins separated by an insulating region. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets disposed on the second fin. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first strained layer is disposed on the first fin adjacent to the first stack of semiconductor nanosheets. The second strained layer is disposed on the second fin adjacent to the second stack of semiconductor nanosheets. The blocking wall is disposed on the insulating region and located between the first and second strained layers. The top surface of the blocking wall is higher than the top surface of the first strained layer or the second strained layer.