Nanosheet Gate Metal Stack for Boundary Loss and Patterning Space
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Solution Overview
Problem
In semiconductor device fabrication, the scaling down of transistor devices leads to significant boundary loss of the metal gate along the longitudinal axis, and insufficient space for patterning the metal gate, making it challenging to maintain the integrity of the gate structure.
Innovation Solution
A method is introduced where a first work function metal layer fills the sheet-to-sheet space between nanostructures and a second work function metal layer with thin thickness wraps around the nanostructures, preventing boundary loss and ensuring sufficient space for patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but the metal gate structure experiences significant boundary loss and insufficient patterning space
Solution Approach 1:
The metal gate structure is segmented into multiple layers: a first work function metal layer filling sheet-to-sheet spaces between nanostructures, and a second work function metal layer wrapping around the nanostructures. This segmentation allows each layer to serve specific functions in maintaining gate integrity during scaling.
Solution Approach 2:
The first work function metal layer is nested within the sheet-to-sheet spaces between nanostructures, while the second work function metal layer is nested around the nanostructures. This nested configuration enables both layers to contribute to preventing boundary loss simultaneously.
2Ease of operation
If the metal gate thickness is reduced to enable patterning, then sufficient space for patterning is achieved, but boundary loss of the metal gate increases
Solution Approach 1:
Different regions of the metal gate structure have different layer configurations: the first work function metal layer is localized in sheet-to-sheet spaces where it prevents boundary loss, while the second work function metal layer is localized around nanostructures where it enables patterning. This local quality differentiation resolves the contradiction between thickness reduction and boundary loss prevention.
Data Source
AI summary
A semiconductor device includes nanostructures extending in a first direction above a substrate and spaced apart in a second direction perpendicular to the first direction, a gate dielectric layer wrapping around each of the nanostructures, a first p-type work function metal layer between the adjacent nanostructures, a second p-type work function metal layer in contact with opposite sidewalls of the first p-type work function metal layer and opposite sidewalls of the gate dielectric layer, and an n-type work function metal layer covering the second p-type work function metal layer. The second p-type work function metal layer comprises a main layer and a cap layer over the main layer, wherein the cap layer has a material different from a material of the main layer.