Nanosheet Gate Structure with Oxide Sacrificial Layers for Cell Isolation
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Solution Overview
Problem
Existing multi-gate devices, such as FinFETs and gate-all-around transistors, face challenges in achieving the desired scaling and increased density due to issues with gate pitch reduction and leakage current, which current fabrication schemes have not adequately addressed.
Innovation Solution
A method involving the use of nanosheet devices with oxide sacrificial layers, where semiconductor layers are interleaved with sacrificial layers to form fin structures, followed by replacement with active gate structures, enabling precise control of gate pitch and isolation, thereby improving device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate pitch is reduced to increase device density, then device density improves, but leakage current between transistors increases
Solution Approach 1:
The patent divides the gate structure into multiple segments with isolation regions between adjacent transistors. The isolation regions are formed by removing sacrificial layers from between the gates, creating physical separations that prevent leakage current while maintaining reduced gate pitch for high device density.
Solution Approach 2:
The patent extracts the isolation function from the gate structure by removing sacrificial layers between adjacent gates. This creates discrete isolation regions that eliminate leakage paths while preserving the compact gate pitch arrangement, solving the contradiction between density and leakage prevention.
2Length of moving object
If continuous poly on diffusion edge (CPODE) structures are used to scale gate pitch, then gate pitch scaling is achieved, but device density and cell isolation are insufficient
Solution Approach 1:
The patent segments the continuous gate structure by removing sacrificial layers between adjacent transistors, creating isolation regions. This segmentation maintains the scaled gate pitch while improving device density through better cell isolation, overcoming the limitations of CPODE structures.
Solution Approach 2:
The patent introduces a vertical dimension to the gate structure by forming isolation regions that extend between gates. This dimensional approach enables effective cell isolation in scaled devices without compromising the reduced gate pitch, achieving both compactness and isolation.
3Quantity of substance
If multi-gate devices are implemented to increase density, then device density improves, but fabrication challenges increase
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial layers between gates before completing the gate structure. These sacrificial layers are later removed to create isolation regions, simplifying the overall fabrication process for multi-gate devices while maintaining high device density.
Solution Approach 2:
The patent uses sacrificial layers as intermediary materials during fabrication. These temporary structures facilitate the formation of isolation regions between gates, reducing fabrication complexity for multi-gate devices while enabling high device density through precise isolation control.
Data Source
AI summary
A method includes forming a fin protruding from a substrate, where the fin includes semiconductor layers interleaved with dielectric sacrificial layers. The method includes forming inner spacers at end portions of each of the dielectric sacrificial layers. The method includes forming source/drain features in the fin adjacent to the inner spacers. The method includes removing a portion of the fin between adjacent source/drain features to form a trench. The method includes forming an isolation structure in the trench.