Nanosheet Gate Electrode Structure for Channel Thickness Control
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with scaling down, leading to higher manufacturing costs and complexity.
Innovation Solution
A semiconductor device structure is manufactured using a stack of semiconductor layers with alternating first and second layers of different etch selectivity, fin formation, and gate electrode layer formation, along with dielectric and sacrificial gate stack processes, to create nanosheet transistors with optimized channel and gate configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases
Solution Approach 1:
The semiconductor structure is divided into multiple alternating layers of first and second semiconductor materials with different etch selectivities. This segmentation allows for independent processing and formation of nanosheet channels through selective removal of sacrificial layers, enabling precise control at reduced geometry sizes while managing processing complexity through modular fabrication steps.
Solution Approach 2:
Different regions of the semiconductor structure are assigned different material compositions and properties. The first and second semiconductor layers have different etch selectivities, allowing localized processing where sacrificial layers can be selectively removed to form nanosheet channels in specific regions while maintaining other structures intact, thus reducing overall processing complexity.
2Quantity of substance
If functional density is increased by scaling down, then more circuits fit per chip area, but manufacturing complexity increases
Solution Approach 1:
The chip is divided into multiple nanosheet channels formed by alternating semiconductor layers. Each layer pair can be processed independently through selective etching of sacrificial materials, allowing high functional density through parallel fabrication of multiple channels while maintaining manageable manufacturing complexity through repeated modular steps.
Solution Approach 2:
The invention transitions from planar device structures to three-dimensional nanosheet channels formed by alternating layers. This vertical stacking in the third dimension increases the number of circuits per chip area without proportionally increasing manufacturing complexity, as the same fabrication processes are applied repeatedly in the vertical direction.
3Productivity
If geometry size is reduced, then production efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The semiconductor structure uses layers of different materials with distinct etch selectivities. This allows precise control of nanosheet channel thickness through selective removal of sacrificial layers, as the etching process can be precisely controlled to remove only the sacrificial material while leaving the semiconductor channels intact, achieving high manufacturing precision at reduced geometry sizes.
Solution Approach 2:
Sacrificial layers of semiconductor material are introduced as intermediary elements between the final semiconductor channels. These sacrificial layers have different etch selectivity and can be selectively removed to define the final channel geometry. This intermediary approach enables precise control of channel thickness through the thickness of the sacrificial layers, which can be accurately controlled during deposition.
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.