Recessed Fin Isolation Layout for Gate Contact in Nanosheet ICs
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in maintaining mobility improvement and short channel control as device dimensions scale below the 10 nanometer node, particularly in multi-gate transistors like tri-gate transistors, where lithographic processes face constraints due to the trade-off between feature dimension and spacing, and the complexity of fin trim isolation (FTI) processes increases with shrinking gate pitch and Fin pitch.
Innovation Solution
The implementation of a 'plug-last' approach in integrated circuit structures, where the metal gate cut process is performed after gate dielectric and work function metal deposition, and the formation of fin isolation regions is recessed to accommodate gate contacts, using an isotropic etch to remove the metal gate and dielectric fill, reducing capacitive coupling and improving SRAM performance by replacing large conductive structures with dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to increase density, then the number of functional units per chip increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar transistors to multi-gate transistors (tri-gate, gate-all-around), adding vertical gating dimensions to control the channel. This dimensional change provides superior electrostatic control and short channel effect suppression at scaled dimensions while maintaining high device density through efficient space utilization.
2Productivity
If feature size is reduced to increase functional unit density, then more devices fit on chip, but lithographic process constraints increase due to trade-off between critical dimension and spacing
Solution Approach 1:
The patent segments the gate structure into multiple gates (multi-gate transistors) that wrap around the channel, allowing each gate segment to be controlled independently. This segmentation enables effective channel control at smaller dimensions while the modular structure simplifies lithographic patterning compared to attempting to pattern entire channels at reduced dimensions.
3Productivity
If fin pitch and gate pitch are reduced to increase device density, then more devices fit on chip, but fin trim isolation process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the complete multi-gate structure and establishing proper isolation regions before final gate patterning and trimming steps. This sequence allows fin pitch and gate pitch to be reduced while maintaining process simplicity, as the isolation structures are already in place to guide subsequent precise patterning operations.
4Ease of manufacture
If conventional metal gate fill process is used, then gate electrodes are formed, but voids may occur during metal fill affecting work function metal deposition
Solution Approach 1:
The patent performs preliminary gate dielectric deposition and gate electrode formation with optimized parameters before work function metal deposition. This preliminary action ensures complete, void-free metal fill in the gate structure, providing a uniform substrate for subsequent work function metal deposition and ensuring precise electrical characteristics.
5Ease of manufacture
If large conductive structures are used in isolation regions, then device fabrication is simplified, but capacitive coupling between devices increases reducing SRAM performance
Solution Approach 1:
The patent changes the material parameter of isolation region structures from conductive to dielectric materials. This parameter change eliminates parasitic capacitive coupling between adjacent devices while maintaining the isolation function, thereby improving SRAM performance through reduced leakage and improved signal integrity without significantly complicating the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitive coupling between devices, enhances SRAM performance, and ensures seamless work function metal deposition by avoiding voids during metal fill, while maintaining effective endcap spacing and reducing processing complexity.
Implementation Method 1
using an isotropic etch to remove the metal gate and dielectric fill
Implementation Method 2
reducing capacitive coupling and improving SRAM performance by replacing large conductive structures with dielectric materials
Data Source
AI summary
Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.