Nanosheet Gate Contact Layout for Wider Backside Process Margins
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Solution Overview
Problem
Existing semiconductor devices face challenges in securing process margins for forming gate contacts, source/drain contacts, and bottom vias, and simplifying the processes involved.
Innovation Solution
A semiconductor device design featuring a first lower interlayer insulating layer, insulating patterns, nanosheets, and gate electrodes with integrated source/drain and gate contacts, allowing for the formation of contacts and vias in a backside region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate contacts, source/drain contacts, and bottom vias are formed separately through multiple processes, then each contact can be precisely positioned, but the process complexity increases and process margins are difficult to secure
Solution Approach 1:
The patent combines the formation of gate contacts, source/drain contacts, and bottom vias into a single integrated contact structure. This is achieved by forming a unified contact hole that simultaneously accommodates all three contact types, and filling it with a single conductive material layer that serves multiple functions. This merging approach reduces the number of separate formation processes while maintaining precise positioning through the unified structure design.
Solution Approach 2:
The integrated contact structure serves multiple functions simultaneously: it provides electrical connection for gate contacts, source/drain contacts, and bottom vias through a single structure. The unified contact hole and conductive material layer are designed to accommodate and connect all three contact types, making the structure universal for multiple electrical connection purposes and simplifying the overall fabrication process.
2Ease of manufacture
If multiple separate processes are used to form gate contact, source/drain contact, and bottom via, then each structure can be optimized independently, but manufacturing time and process steps increase
Solution Approach 1:
The patent merges the formation of gate contact, source/drain contact, and bottom via into a single integrated process step. Instead of forming each contact separately through multiple etching and filling operations, the invention creates one unified contact hole structure and fills it in a single operation. This combining approach maintains ease of manufacture through standardized processes while dramatically improving productivity by reducing the total number of process steps and manufacturing time.
3Ease of operation
If gate contact and source/drain contact are formed as separate structures, then each contact can be independently controlled, but the process margin for forming all contacts is reduced
Solution Approach 1:
The patent combines the formation of gate contact and source/drain contact into a single integrated contact structure with unified dimensions and positioning. This merging eliminates the need for separate process control for each contact type, thereby increasing the process margin. The unified structure ensures that all contacts are formed simultaneously with consistent dimensional control, reducing variability and improving reliability while maintaining ease of operation through standardized formation processes.
Data Source
AI summary
A semiconductor device comprising a first lower interlayer insulating layer, an insulating pattern extending in a first horizontal direction, a first and second plurality of nanosheets stacked apart from one another in a vertical direction, a first gate electrode extending in a second horizontal direction, the first gate electrode surrounding the first plurality of nanosheets, a second gate electrode extending in the second horizontal direction, the second gate electrode surrounding the second plurality of nanosheets, a source/drain region between the first and second gate electrodes, a source/drain contact penetrating the first lower interlayer insulating layer and the insulating pattern, the source/drain contact electrically connected to the source/drain region, and a gate contact penetrating the first lower interlayer insulating layer and the insulating pattern, the gate contact electrically connected to the second gate electrode, at least a portion of a sidewall of the gate contact contacting the source/drain contact.