Nanosheet Gate Cut Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Integrated circuit (IC) devices face challenges in preventing undesired parasitic capacitance and short circuits as they scale down, requiring improved structural designs to maintain high operating speed and accuracy.
Innovation Solution
The IC device incorporates fin-type active regions with nanosheet stacks surrounded by a gate line, featuring a gate cut insulating portion and corner insulating spacers made of materials like silicon nitride or silicon oxide, which reduce the length of the gate line and prevent leakage currents, thereby minimizing parasitic capacitance and short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device size is scaled down to improve integration density, then productivity increases, but parasitic capacitance and short circuit risks increase
Solution Approach 1:
The patent introduces corner insulating spacers as intermediary elements positioned at the corners where the gate line contacts the device isolation film. These spacers act as mediators that electrically isolate the gate line from adjacent conductive regions, preventing parasitic capacitance formation and short circuits while enabling continued device downscaling
Solution Approach 2:
The gate line structure is segmented by introducing gate cut insulating portions and corner insulating spacers that divide the continuous gate line into isolated sections. This segmentation prevents unwanted electrical coupling between adjacent gate lines and conductive regions, reducing parasitic capacitance effects
2Productivity
If the device size is scaled down to improve integration density, then productivity increases, but short circuit risks increase
Solution Approach 1:
Corner insulating spacers serve as intermediary barrier elements that physically and electrically separate the gate line from adjacent conductive regions. This intermediary structure prevents direct contact and potential short circuits while maintaining the compact scaled-down device layout
Solution Approach 2:
The corner insulating spacers are formed in advance during the manufacturing process to provide pre-established electrical isolation. This beforehand cushioning prevents short circuit risks before they can occur, ensuring reliability in scaled-down devices
3Reliability
If aspect ratios of components are increased to maintain functionality in scaled devices, then device performance is maintained, but parasitic capacitance increases
Solution Approach 1:
The corner insulating spacers act as intermediary elements that break up continuous conductive paths at critical corner regions. This mediation reduces the effective area for parasitic capacitance formation even when component aspect ratios are increased to maintain functionality in scaled devices
Data Source
AI summary
An integrated circuit device includes fin-type active regions extending in a first lateral direction on a substrate, a device isolation film covering sidewalls of the fin-type active regions, a gate line on the fin-type active regions and the device isolation film, nanosheet stacks on a fin top surface of each of the fin-type active regions, each nanosheet stack including at least one nanosheet and being surrounded by the gate line, a gate cut insulating portion on the device isolation film and facing an end sidewall of the gate line in a second lateral direction, and a corner insulating spacer between a first nanosheet stack of the nanosheet stacks and the gate cut insulating portion and between the device isolation film and the gate line, the first nanosheet stack being closest to the gate cut insulating portion in the second lateral direction.