Nanosheet Gate Structure With Dielectric Wall for Lower Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) geometry, leading to increased complexity and production costs, while maintaining efficient production and reducing resistance in gate structures.
Innovation Solution
The formation of semiconductor devices with multi-gate transistors, such as FinFET devices, gate-all-around (GAA) devices, and strained-semiconductor structures, utilizing nanosheet mesas, dielectric walls, and gate structures with recesses to reduce resistance and improve connectivity, along with epitaxial layers and vertical gate contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If photolithography and self-aligned processes are used to scale down geometry, then production efficiency and cost are improved, but manufacturing precision and device complexity increase due to smaller pitches and reduced geometry
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning or multi-patterning techniques. This allows the formation of complex nanosheet structures with precise pitch control by breaking down single-step lithography into sequential patterning operations, thereby maintaining manufacturing precision while enabling scalable production
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional nanosheet structures with gate-all-around configuration. This dimensional change enables improved electrostatic control and device performance while maintaining compatibility with standard photolithography processes, addressing both productivity and precision requirements
2Productivity
If geometry size is reduced to increase functional density, then production efficiency is improved, but device complexity increases due to smaller and more complex circuits
Solution Approach 1:
The patent employs vertical stacking of multiple semiconductor nanosheets to create three-dimensional device structures. This approach increases functional density by utilizing the vertical dimension rather than solely reducing lateral dimensions, thereby improving production efficiency while managing circuit complexity through standardized vertical integration
Solution Approach 2:
The gate structure completely surrounds each semiconductor nanosheet in a nested configuration, with the gate wrapping around the channel from all sides. This gate-all-around structure provides enhanced electrostatic control over the channel while maintaining a compact footprint, addressing both productivity and device complexity challenges
3Ease of operation
If advanced patterning techniques are used to create smaller pitches, then connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses preliminary patterning steps to define mandrel structures before forming the final nanosheet patterns. These preliminary structures serve as templates that guide subsequent self-aligned etching processes, ensuring precise pattern transfer and connectivity while reducing the precision demands on final lithography steps
Solution Approach 2:
The patent introduces dielectric walls as intermediary structures that separate and define the nanosheet regions. These dielectric structures act as placeholders and alignment references during fabrication, enabling precise connectivity formation while managing the complexity of advanced patterning processes
Data Source
AI summary
A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.