Nanosheet Gate Dielectric Fluorination for Vacancy Passivation
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining reliability and mobility, particularly in the formation of gate dielectrics and semiconductor layers.
Innovation Solution
The introduction of a fluorine treatment process for gate dielectrics, involving a fluorine-containing layer deposition and annealing to diffuse fluorine into the gate dielectrics, enhances the effective oxide thickness and improves the reliability and mobility of semiconductor devices by filling vacancies and attaching to dangling bonds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fluorine treatment process is introduced to improve gate dielectric performance, then reliability and mobility are improved, but device complexity increases
Solution Approach 1:
The fluorine treatment process is segmented into distinct stages: depositing fluorine-containing material, annealing to diffuse fluorine, and removing excess fluorine. This segmentation allows each stage to be optimized independently while maintaining overall process control and improving gate dielectric reliability systematically.
Solution Approach 2:
Fluorine-containing material is deposited and annealed in advance before final gate dielectric formation is completed. This preliminary fluorine incorporation prepares the gate dielectric structure for subsequent processing steps, ensuring improved reliability is built into the foundation of the device architecture.
2Productivity
If minimum feature size is reduced to increase integration density, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The fluorine treatment process introduces new controllable parameters (fluorine concentration, annealing temperature, annealing time) that can be precisely adjusted to achieve desired gate dielectric properties. These additional parameters provide fine-tuning capability that compensates for the reduced tolerance margins inherent in smaller feature sizes, maintaining manufacturing precision while enabling higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process results in improved semiconductor device yield and robustness by tuning voltage and enhancing the performance of gate dielectrics, addressing the challenges of miniaturization in semiconductor manufacturing.
Implementation Method 1
performing an anneal process on the fluorine-containing layer, wherein performing the anneal process includes diffusing fluorine from the fluorine-containing layer into the gate dielectric
Data Source
AI summary
A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive