Nano-Sheet Gate Gap Fill Using Oxide Interposer Spacing

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Solution Overview

Problem

The challenge of managing and improving the performance of densely packed semiconductor devices, particularly nanostructure field-effect transistors (nano-FETs), is exacerbated by issues such as silicon-germanium intermixing and metal gate extrusion, leading to defects and reduced electrical performance.

Innovation Solution

The use of a Disposable Oxide Interposer (DOI) process, which replaces silicon germanium with oxide materials like silicon dioxide or silicon oxynitride, combined with gradient oxidation and selective etching, to maintain nanostructure shape and facilitate improved work function metal filling, reducing defects and enhancing electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If silicon germanium is used as sacrificial material in multi-layer stacks, then the sacrificial material can be selectively removed to form nanostructures, but silicon-germanium intermixing occurs leading to defects and reduced electrical performance

Engineering Contradiction:

Improvenanostructure formation precisionVSAvoidelectrical performance

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent uses oxide materials (silicon oxide, silicon oxynitride) as disposable sacrificial materials that are removed after serving their purpose of defining nanostructure spaces. These oxide layers are deposited, patterned, and etched to create precise nanostructure geometries, then completely removed to eliminate intermixing defects. The sacrificial oxide layers are 'cheap' in terms of process complexity and 'short-living' as they are intentionally removed after forming the nanostructure pattern.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

2Productivity

If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional problems such as silicon-germanium intermixing and metal gate extrusion arise

Engineering Contradiction:

Improveintegration densityVSAvoiddevice performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent introduces oxide materials as intermediary sacrificial layers between the deposition and final nanostructure formation steps. These oxide intermediaries enable precise patterning at reduced feature sizes without direct contact between silicon and germanium layers that would cause intermixing. The oxide mediator is deposited conformally, patterned with lithography, and selectively removed to define clean nanostructure interfaces.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If work function metal layers are deposited to fill sheet-to-sheet spacing, then gate electrodes can be formed, but gap fill challenges persist in high aspect ratio structures

Engineering Contradiction:

Improvemetal layer fill completenessVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by depositing oxide sacrificial layers and forming spacer structures before depositing the work function metal layers. The oxide layers are removed to create open spaces, and spacers are formed to define precise gaps. This preliminary structuring ensures that when work function metal is deposited, it can properly fill the defined spaces without voids or incomplete coverage, solving the gap fill challenge before the metal deposition step.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in nano-FETs with lower resistance, higher drive currents, and reduced channel resistance, while minimizing punch-through defects and ensuring full metal-cap film coverage, thereby improving device performance and reliability.

Implementation Method 1

The oxide material is selectively removed to form spaces between adjacent second nanostructures

Methodology Applied

Scientific EffectSelective etching:

Implementation Method 2

forming a first work function metal layer around each of the at least two second nanostructures; forming a second work function metal layer around each of the at least two second nanostructures

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS20260082668A1Gap fill approach for high aspect ratio sheet-sheet spacing on nano-sheet structure

Publication Date: 2026.03.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device and method of forming is provided. The method includes forming a first work function metal layer around a first nanostructure in a fin disposed over a substrate, oxidizing at least a portion of the first work function metal layer, where less of the work function metal layer is oxidized between the first nanostructure and an adjacent second nanostructure in a stack in the fin, removing oxidized portions of the first work function metal layer from around the first nanostructure, and forming a second work function metal layer around the first nanostructure, where the first work function metal layer and the second work function metal layer fill a void between the first nanostructure and the adjacent second nanostructure.