Nanosheet Gate Structure for Metal Height Control and Lower Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling metal gate heights and reducing device capacitance as minimum feature size reduces, impacting integration density and device performance.
Innovation Solution
A method for manufacturing semiconductor devices involving the formation of nanosheet stacks with alternating semiconductor and spacing layers, followed by fin structure formation, isolation, and replacement gate processes to achieve precise control over gate heights and reduce device capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but control over metal gate heights becomes challenging and device capacitance increases
Solution Approach 1:
The gate structure is segmented into multiple distinct layers: a metal gate layer and a separate fill layer. This segmentation allows independent processing and height control of each layer, enabling precise metal gate height control even as feature sizes reduce and integration density increases.
Solution Approach 2:
The patent introduces a vertical dimension solution by creating a two-layer gate structure where the metal gate layer and fill layer are stacked vertically. This dimensional approach allows the metal gate height to be controlled independently of the overall gate structure, resolving the manufacturing precision challenge while maintaining high integration density.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but device capacitance increases
Solution Approach 1:
A dielectric fill layer is introduced as an intermediary between the metal gate layer and the channel. This fill layer acts as a mediator that reduces parasitic capacitance between the gate and channel, allowing high integration density to be achieved without the penalty of increased device capacitance.
Solution Approach 2:
The gate structure is given non-uniform local quality through the two-layer configuration, where the fill layer provides different electrical properties (lower capacitance) in specific regions. This local differentiation reduces overall device capacitance while maintaining the high integration density enabled by reduced feature sizes.
3Ease of manufacture
If conventional single-layer gate structure is used, then manufacturing is simpler, but control over metal gate heights is challenging at reduced feature sizes
Solution Approach 1:
The gate structure is divided into manufacturable segments: a metal gate layer formed by deposition and a fill layer formed by a separate filling process. This segmentation maintains manufacturing simplicity through standard deposition and filling techniques while achieving precise height control that would be difficult with a conventional single-layer structure.
Data Source
AI summary
Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control.