Nanosheet Gate Transistor Structure for Dense IC Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) technology while maintaining efficient production and reducing costs, particularly in the formation of transistors and memory devices, where the complexity and density of circuits increase with decreasing geometry size, leading to difficulties in transistor design and integration.
Innovation Solution
The development of a manufacturing method for integrated circuits that includes the formation of second transistors with nanosheet gate structures, where first and second material layers are alternately stacked and patterned to create nanosheets, which increase the contact area between the channel layer and the gate structure, enhancing electrical performance, and are integrated within the interconnection structure alongside memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor geometry size is decreased to increase functional density, then production efficiency and cost are improved, but transistor design and integration become more difficult
Solution Approach 1:
The gate structure is segmented into multiple nanosheets stacked vertically, creating a three-dimensional architecture that increases effective channel width without increasing planar footprint. This segmentation allows the transistor to maintain higher functional density while simplifying the integration process by using standardized stacked building blocks
Solution Approach 2:
The invention transitions from two-dimensional planar transistors to three-dimensional nanosheet stacked transistors, utilizing the vertical dimension to increase effective channel width. This dimensional change enables continued scaling benefits while improving transistor performance and easing integration constraints
2Quantity of substance
If transistor geometry size is decreased to increase functional density, then more circuits can be integrated per chip area, but manufacturing precision requirements increase
Solution Approach 1:
The gate is divided into multiple discrete nanosheets that can be formed through sequential deposition and etching steps. Each nanosheet layer can be manufactured with standard precision requirements, avoiding the need for ultra-precise single-layer fabrication while achieving high functional density through vertical stacking
Solution Approach 2:
Multiple nanosheet layers are nested vertically within the same planar footprint, with each layer containing a complete gate structure. This nesting approach allows high circuit density to be achieved through vertical integration rather than lateral scaling, reducing manufacturing precision demands
3Reliability
If nanosheet gate structures are formed with multiple stacked material layers, then contact area between channel layer and gate structure increases, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple thin nanosheet layers stacked vertically, each contributing to the total gate-channel contact area. This segmentation increases the effective interface between gate and channel, improving electrical control and performance while maintaining manageable structural complexity through repetitive modular units
Solution Approach 2:
The stacked gate structure employs composite material layers including semiconductor nanosheets, dielectric materials, and conductive gates. This composite approach enables optimized electrical performance through material selection while the regular stacked pattern keeps fabrication complexity manageable
Data Source
AI summary
A transistor includes a first gate structure, a channel layer, and source/drain contacts. The first gate structure includes metallic nanosheets and a gate dielectric layer wrapping around the metallic nanosheets. The channel layer wraps around a portion of the gate dielectric layer. The source/drain contacts are aside the metallic nanosheets. The source/drain contacts are electrically connected to the channel layer.