Inter-Region Insulation Layout for Nanosheet Gate Reliability
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Solution Overview
Problem
As integrated circuit devices shrink in size, the integration density of field-effect transistors increases, posing challenges in maintaining the performance and reliability of horizontal nanosheet field-effect transistors (hNSFETs) due to defects in the manufacturing process and inter-region insulation.
Innovation Solution
The integrated circuit device incorporates a substrate with fin active regions, isolation films, gate cut insulating patterns, and inter-region insulating patterns, where the inter-region insulating pattern partially penetrates the gate line in a vertical direction, enhancing insulation and reducing manufacturing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of integrated circuit device is decreased to increase integration density, then the number of transistors per unit area increases, but manufacturing defects and inter-region insulation problems worsen
Solution Approach 1:
The device is divided into multiple device regions separated by inter-region insulating patterns. These patterns segment the continuous substrate into isolated functional regions, preventing defect propagation between regions while maintaining high integration density through compact arrangement of multiple regions.
Solution Approach 2:
Inter-region insulating patterns serve as intermediary structures between adjacent device regions. These insulating patterns act as mediators that electrically isolate regions while allowing close proximity placement, thus enabling high integration density without compromising reliability through inter-region interference or defect propagation.
2Reliability
If inter-region insulating pattern partially penetrates gate line in vertical direction, then insulation between regions is enhanced, but manufacturing complexity increases
Solution Approach 1:
The insulating pattern extends in the vertical dimension by partially penetrating the gate line structure. This vertical extension provides enhanced insulation between device regions without requiring additional lateral space, thus improving reliability while maintaining compact device footprint and relatively simple manufacturing processes.
3Reliability
If gate line length is limited by gate cut insulating patterns, then inter-region interference is reduced, but transistor performance control becomes more difficult
Solution Approach 1:
Gate cut insulating patterns are strategically placed at specific locations to limit gate line length only where inter-region interference occurs. This localized approach maintains appropriate gate line lengths for transistor performance in critical regions while providing isolation where needed, thus balancing reliability improvement with performance control through selective application.
Data Source
AI summary
An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.