Nanosheet Gate Isolation Structure for Current Control in Tight Layouts
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Solution Overview
Problem
Existing multi-gate devices face challenges in reducing device area while maintaining performance, particularly in advanced technology nodes, as conventional methods for adjusting current levels in nanosheet devices often require additional area and complexity.
Innovation Solution
The introduction of two-dimensional gate isolation structures that partially truncate the active region of MOS devices, incorporating horizontal and transverse portions to reduce the active region's width and adjust current levels without increasing device footprint, achieved through modifications to existing structural features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional methods are used to adjust current levels in nanosheet devices, then current control is achieved, but device area increases and fabrication complexity increases
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate, second gate, third gate) that can independently control different portions of the channel. This segmentation enables fine-grained current control without requiring additional device area, as the control is achieved through spatial division of existing gate structures rather than adding new components.
Solution Approach 2:
The invention transitions from planar gate control to three-dimensional gate-all-around structures that wrap around the nanosheet channels. This dimensional change enables superior electrostatic control and current modulation in the vertical dimension, achieving better current control density without increasing the lateral device footprint.
2Ease of operation
If conventional methods are used to adjust current levels in nanosheet devices, then current control is achieved, but fabrication complexity increases
Solution Approach 1:
The gate structures serve multiple functions: they provide electrical control over the channel, act as isolation structures between adjacent devices, and define active regions. This multi-functionality reduces fabrication complexity by eliminating the need for separate isolation and control structures, as the gates perform both control and isolation roles simultaneously.
Solution Approach 2:
The invention merges the gate control function with the isolation function into a single integrated structure. The gate isolation structures are formed as part of the same fabrication sequence as the gates themselves, combining what would traditionally be separate fabrication steps into a unified process, thereby reducing overall fabrication complexity.
3Area of stationary object
If device area is reduced in advanced technology nodes, then device density increases, but maintaining performance becomes more difficult
Solution Approach 1:
The nanosheet channels are nested within gate structures that completely surround them in three dimensions. This nested gate-all-around configuration provides superior electrostatic control over the channel, enabling high-performance operation in reduced device areas by maximizing the gate's control efficiency per unit area through complete spatial enclosure of the active channel.
Data Source
AI summary
A semiconductor structure includes a semiconductor fin protruding from a substrate and extending across the substrate along a first lateral direction. The semiconductor structure includes a plurality of gate structures disposed over the substrate, where each gate structure extends along a second lateral direction perpendicular to the first lateral direction. The semiconductor structure includes a gate isolation structure disposed over the gate structures. The gate isolation structure including a first portion and a second portion connected to the first portion. The first portion extends over the gate structures along the first lateral direction. The second portion partially extends into the semiconductor fin along the second lateral direction.