Nanosheet Gate Isolation Structure for Etch Undercut Control
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Solution Overview
Problem
In semiconductor device fabrication, the close N-to-P spacing of fork-sheet FETs leads to smaller patterning process margins, increasing the likelihood of gate etch undercutting, which can cause NFET work function metals to encroach onto PFET channels, negatively impacting device performance.
Innovation Solution
Incorporating an etch-stop isolation (ESI) region over the nanosheet stack to prevent undercutting during gate etch operations, ensuring that the gate element between the ESI region and the nanosheet stack remains intact and preventing electrical contact between the nanosheet stack and adjacent gate elements with different work function metals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fork-sheet FETs are fabricated with close N-to-P spacing to increase device density, then device density is improved, but patterning process margins are reduced leading to increased gate etch undercutting
Solution Approach 1:
An etch-stop isolation (ESI) region is formed over the nanosheet stack before gate etch operations. This preliminary structural preparation creates a protective barrier that prevents gate etch undercutting from exposing the nanosheet stack, thereby enabling close N-to-P spacing while maintaining sufficient patterning process margins.
Solution Approach 2:
The ESI region acts as an intermediary protective layer between the gate element and the nanosheet stack. During gate etch operations, this intermediate structure absorbs the undercutting effect, preventing direct exposure of the nanosheet stack and enabling tighter device spacing without compromising manufacturing precision.
2Adaptability or versatility
If gate etch operations are performed to form NFET and PFET work function metals, then transistor functionality is achieved, but gate etch undercutting exposes the nanosheet stack and negatively impacts device performance
Solution Approach 1:
The ESI region serves as a protective intermediary structure positioned over the nanosheet stack. During necessary gate etch operations for forming NFET and PFET work function metals, this intermediate layer absorbs the undercutting effect, preventing exposure of the nanosheet stack and thereby maintaining device performance while enabling transistor functionality.
Solution Approach 2:
The ESI region is formed beforehand to cushion against the harmful effects of gate etch undercutting. This prior protective measure ensures that even when gate etch operations are performed to achieve transistor functionality, the nanosheet stack remains protected and device performance is maintained.
3Adaptability or versatility
If NFET and PFET are integrated in the same structure with different work function metals, then device integration is improved, but gate etching operations cause metal encroachment between adjacent transistors
Solution Approach 1:
The structure is segmented into distinct regions with the ESI region forming a protective barrier between NFET and PFET areas. This segmentation allows different work function metals to be deposited and etched for each transistor type while preventing metal encroachment between adjacent transistors, thereby maintaining both device integration and manufacturing precision.
Solution Approach 2:
The ESI region acts as an intermediary barrier between NFET and PFET structures. During gate etching operations for different work function metals, this intermediate structure prevents metal encroachment between adjacent transistors, enabling high device integration while maintaining precise metal placement control.
Data Source
AI summary
Embodiments of the invention are directed to an integrated circuit (IC) that includes a channel that includes a nanosheet stack; an etch-stop isolation (ESI) region over the nanosheet stack; and a portion of a first type of gate element between the ESI region and the nanosheet stack. The ESI region is operable to prevent etching the portion of the first type of gate element that is between the ESI region and the nanosheet stack.