Nanosheet Gate Structure With Isolation to Reduce Leakage
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing complexity.
Innovation Solution
The process involves forming FinFET and gate all-around (GAA) transistor structures using double-patterning or multi-patterning techniques, which include forming sacrificial layers, spacers, and using epitaxial growth to create semiconductor stacks with alternating layers for etching selectivity and oxidation rate differences, along with the formation of isolation structures and metal gate stacks to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (double-patterning or multi-patterning techniques) where each step creates a portion of the final pattern. This segmentation allows achieving smaller feature sizes through sequential simpler operations rather than attempting to create all features in a single complex step, thereby improving productivity while managing fabrication complexity.
Solution Approach 2:
Sacrificial layers are formed in advance before the final pattern is created. These preliminary structures serve as templates or guides for subsequent patterning steps, enabling precise feature formation at smaller dimensions while simplifying the overall fabrication process by pre-establishing critical geometries.
2Productivity
If feature sizes decrease to increase functional density, then chip area utilization is improved, but manufacturing reliability deteriorates
Solution Approach 1:
Sacrificial layers act as intermediary structures that facilitate the formation of final patterns at smaller feature sizes. These intermediate structures provide mechanical support and process control during fabrication, enabling high functional density while maintaining manufacturing reliability by serving as temporary guides and templates that can be precisely controlled and subsequently removed.
Solution Approach 2:
The patent employs multiple patterning techniques that change process parameters across different fabrication steps. By varying exposure conditions, etching parameters, and material properties across sequential steps, the process achieves smaller feature sizes with controlled precision, thereby improving functional density while maintaining manufacturing reliability through parameter optimization at each stage.
3Length of moving object
If advanced patterning techniques are used to create smaller features, then feature size is reduced, but process complexity increases
Solution Approach 1:
The complex task of creating small features is segmented into multiple simpler patterning operations. Each patterning step creates a subset of the final pattern using standard lithographic techniques, avoiding the need for single-step ultra-fine patterning. This segmentation reduces processing complexity while achieving the target feature size through cumulative effect of multiple steps.
Solution Approach 2:
The patent introduces additional process dimensions by using vertical sacrificial layers and multi-layer structures. Instead of attempting to achieve all pattern complexity in a single planar lithography step, the solution adds the vertical dimension with sacrificial layers that are formed, patterned, and removed in sequence, thereby reducing lateral processing complexity while achieving small feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of reliable semiconductor devices with improved performance and reduced complexity by allowing for smaller feature sizes and enhanced etching selectivity, oxidation rates, and reduced current leakage, thereby improving the operation speed and reliability of semiconductor devices.
Implementation Method 1
The semiconductor layers 104a-104d have different etching selectivity than the sacrificial layers 102a-102d
Implementation Method 2
The semiconductor layers 104a-104d have different etching selectivity and/or different oxidation rates than the sacrificial layers 102a-102d
Data Source
AI summary
A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and multiple inner spacers. Each of the inner spacers is between the gate stack and the source/drain epitaxial structure. The semiconductor device structure further includes an isolation structure between the semiconductor fin and the source/drain epitaxial structure.