Nanosheet Gate Isolation Structure for Reduced RC Delay
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Solution Overview
Problem
Nanosheet semiconductor devices face challenges in reducing spacing between oxide-definition regions due to fabrication process variations, affecting threshold voltage and RC time delay, which hinder device performance improvement.
Innovation Solution
A method for manufacturing semiconductor devices involving the formation of isolation layers, dummy poly gates, gate spacers, and recessing processes to define nanosheet stacks, followed by the deposition of high-k materials and metal layers to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between oxide-definition regions is reduced to increase device density, then device functional density is improved, but fabrication process variations cause threshold voltage shifts and increased RC time delay
Solution Approach 1:
A dielectric layer is introduced as an intermediary between adjacent metal gate structures. This dielectric layer acts as a mediator that electrically isolates the metal gates, preventing their electric fields from interacting and causing threshold voltage shifts. The dielectric layer allows the spacing between oxide-definition regions to be reduced for higher device density while maintaining stable threshold voltage by blocking parasitic electric field coupling.
2Productivity
If the spacing between oxide-definition regions is reduced to increase device density, then device functional density is improved, but RC time delay increases due to enhanced short channel effects
Solution Approach 1:
The dielectric layer serves as an intermediary that reduces capacitive coupling between adjacent metal gate structures. By electrically isolating the metal gates, the dielectric layer minimizes parasitic capacitance formation, which directly reduces RC time delay. This allows tighter spacing between oxide-definition regions for higher density while preventing the capacitance increase that would otherwise occur with reduced spacing.
3Productivity
If metal gate structures are placed closer together to increase device density, then functional density is improved, but capacitance between adjacent gates increases
Solution Approach 1:
The dielectric layer is positioned between adjacent metal gate structures as an intermediary that physically separates their electric fields. This intermediary layer reduces the effective capacitive coupling between the metal gates, allowing them to be placed closer together for higher device density without experiencing excessive capacitance. The dielectric material's low dielectric constant further minimizes the capacitance formed between adjacent gates.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a dielectric wall, and a first isolation feature. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure are disposed on the semiconductor substrate. The first semiconductor structure is disposed between the second semiconductor structure and the third semiconductor structure. The dielectric wall is disposed on the semiconductor substrate and is connected between the first semiconductor structure and the second semiconductor structure. The first isolation feature is disposed between the first semiconductor structure and the third semiconductor structure, and extends into the semiconductor substrate.