Nanosheet Gate Isolation Structure for Dense Semiconductor Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with scaling down, requiring innovative methods to enhance production efficiency and reduce costs while maintaining performance.
Innovation Solution
The method involves forming a semiconductor device structure with a stack of semiconductor layers, including alternating first and second semiconductor layers with different etch selectivity, and using advanced processes like epitaxial growth, double-patterning, and etch techniques to create nanosheet transistors with optimized gate and isolation structures, which allows for precise control of channel and gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent segments the gate electrode into multiple discrete gates (first gate electrode, second gate electrode, third gate electrode) that can be independently formed and controlled. This segmentation allows for simplified processing of each individual gate while achieving the overall complex function of multi-gate control, thereby reducing processing complexity despite the advanced device architecture
Solution Approach 2:
The patent transitions from planar 2D transistor structures to three-dimensional nanosheet-based devices with gates extending in multiple spatial dimensions. The nanosheets are formed between dielectric features and surrounded by multiple gates, creating a vertically stacked, multi-dimensional architecture that increases functional density without proportionally increasing processing complexity
2Quantity of substance
If functional density is increased through scaling down, then more interconnected devices fit per chip area, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by first forming the dielectric features (first and second dielectric features) and nanosheets between them before forming any gate electrodes. This preliminary structuring creates a pre-defined template that guides subsequent gate formation processes, simplifying manufacturing by establishing the device framework before adding complex gate structures
Solution Approach 2:
The patent implements a nested structure where nanosheets are positioned between dielectric features, and multiple gate electrodes are formed around and over the nanosheets. The first gate electrode is formed over the nanosheets, the second gate electrode is formed over the first gate electrode, and the third gate electrode is formed over the second gate electrode, creating nested layers that maximize device density within a compact manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-density, complex semiconductor devices with improved performance and reduced manufacturing costs by enhancing processing efficiency and precision in forming nanosheet transistors and isolation structures.
Implementation Method 1
The method involves forming a semiconductor device structure with a stack of semiconductor layers, including alternating first and second semiconductor layers with different etch selectivity, and using advanced processes like epitaxial growth
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.