Nanosheet Gate Isolation Structure for Short-Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistor dimensions continue to scale down, further improvements are needed in nanosheet FETs to address challenges such as short-channel effects and device performance considerations, particularly in achieving steeper sub-threshold current swing and reduced drain-induced barrier lowering.
Innovation Solution
The manufacturing process involves forming a stack of semiconductor layers over a substrate, using epitaxial growth to create nanosheet channels surrounded by a gate electrode, with specific thicknesses and materials chosen for device performance, and incorporating a gate isolation structure to isolate gate electrode layers, thereby enhancing device performance and reducing short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then productivity and production efficiency are improved, but short-channel effects worsen and device performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channel structures where the gate electrode completely surrounds the channel region. This dimensional change enables fuller depletion of the channel and stronger gate control, effectively suppressing short-channel effects while maintaining scaled-down dimensions and high device density.
Solution Approach 2:
The gate electrode is positioned to completely surround and enclose the nanosheet channel region, creating a nested configuration where the gate wraps around the channel from top, bottom, and sidewalls. This nested structure maximizes gate control over the channel, enabling steeper sub-threshold current swing and reduced drain-induced barrier lowering while maintaining small transistor footprints.
2Ease of manufacture
If conventional planar FET structures are used, then manufacturing is simpler, but short-channel effects increase and sub-threshold current swing becomes less steep
Solution Approach 1:
The invention adopts a three-dimensional nanosheet channel structure with gate-all-around configuration, where the gate electrode extends over and under the channel region and contacts sidewalls. This dimensional transformation provides superior electrostatic control and steeper sub-threshold current swing, accepting increased manufacturing complexity as necessary for achieving the required precision in electrical characteristics.
3Productivity
If gate electrode layers are stacked vertically to increase device density, then productivity improves, but interference between adjacent gate layers increases and device reliability decreases
Solution Approach 1:
The patent introduces a gate isolation layer positioned between vertically stacked gate electrode layers. This intermediary structure electrically isolates adjacent gates, preventing unwanted coupling and interference between layers. The gate isolation layer enables dense vertical stacking of multiple nanosheet FETs while maintaining reliable electrical performance and preventing short-channel effects from propagating between layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device performance by reducing short-channel effects and enhancing sub-threshold current swing, leading to more efficient and reliable nanosheet FETs with better scaling capabilities.
Implementation Method 1
forming a stack of semiconductor layers over a substrate, using epitaxial growth to create nanosheet channels
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first gate electrode layer, a second gate electrode layer disposed over and aligned with the first gate electrode layer, and a gate isolation structure disposed between the first gate electrode layer and the second gate electrode layer. The gate isolation structure includes a first surface and a second surface opposite the first surface. At least a portion of the first surface is in contact with the first gate electrode layer. The second surface includes a first material and a second material different from the first material, and at least a portion of the second surface is in contact with the second gate electrode layer.