Nanosheet Gate Line Layout for Insulated High-Density ICs
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Solution Overview
Problem
Current integrated circuit devices face challenges in achieving high integration and performance while maintaining desired functions and operating speed, particularly in designing efficient wiring structures for miniaturized and multifunctional electronic products.
Innovation Solution
The integrated circuit device incorporates a substrate with fin-type active regions, nanosheet stacks, and gate lines arranged in specific configurations, including connected and separated gate lines, vertical structures, and source/drain regions, to enhance performance and reliability by optimizing the layout and insulation between gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate lines are connected across different regions to reduce wiring complexity, then device complexity is reduced, but insulation between gate lines becomes more difficult to maintain
Solution Approach 1:
The gate lines are segmented into connected gate lines in the first region and separated gate lines in the second region. This segmentation allows the gate lines to be connected where needed (reducing complexity) while maintaining separation where insulation is critical (maintaining reliability). The insulating structure is positioned between adjacent gate lines to provide electrical isolation.
Solution Approach 2:
An insulating structure acts as an intermediary element positioned between adjacent gate lines. This intermediary provides electrical insulation between the connected gate lines, preventing unwanted electrical interaction while allowing the gate lines to share a common potential reference, thus resolving the contradiction between connectivity and insulation.
2Quantity of substance
If nanosheet stacks are integrated to increase transistor density, then integration capacity is improved, but interface formation increases causing higher capacitance
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional nanosheet stacks, utilizing the vertical dimension to increase transistor density. Multiple nanosheets are stacked vertically above each fin structure, allowing more transistors to be packed into the same footprint area without proportionally increasing interfac capacitance.
Solution Approach 2:
Multiple nanosheets are nested vertically within each other, forming a stack structure. This nesting arrangement maximizes the use of vertical space to increase transistor density while keeping the horizontal footprint compact, thereby reducing the total interface area exposed to surrounding structures and minimizing capacitance.
3Length of moving object
If fin structures are made smaller to enable miniaturization, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The fin structures and nanosheet stacks are formed using preliminary patterning and etching steps that define the fin geometry before subsequent gate and contact formation. This preliminary structuring establishes precise fin dimensions and positions early in the manufacturing process, enabling miniaturization while maintaining control over dimensional accuracy through established semiconductor fabrication techniques.
Data Source
AI summary
An integrated circuit device includes a first fin and a second fin that extend in a first horizontal direction on a first region of a substrate, a third fin and a fourth fin that extend in the first horizontal direction on a second region of a substrate, a connected gate line at least partially surrounding a first channel region and a second channel region, and a separated gate line including a first separated portion that at least partially surrounds a third channel region and a second separated portion that at least partially surrounds a fourth channel region, where an uppermost portion of a top surface of the separated gate line is at a first vertical level, and an uppermost portion of a top surface of the connected gate line is at a second vertical level higher than the first vertical level.