Nanosheet Gate Structure With Separation Layers for Low Parasitics
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Solution Overview
Problem
The increasing integration of field effect transistors in integrated circuit devices leads to issues with contact resistance and parasitic capacitance, affecting device performance and reliability.
Innovation Solution
The integration circuit device incorporates a fin-type active structure with a nanosheet stack, a gate structure, and a source/drain structure, featuring a silicide separation layer and a silicon separation layer to reduce contact resistance and parasitic capacitance, along with a bottom dielectric isolation and via contacts to enhance electrical connectivity and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of field effect transistors is increased, then the size of integrated circuit elements is reduced, but contact resistance between elements increases
Solution Approach 1:
The source/drain structure is divided into multiple segments including a first source/drain structure, a second source/drain structure, and an intermediate source/drain structure. This segmentation allows for optimized electrical connections at each interface, reducing overall contact resistance while maintaining high integration density.
Solution Approach 2:
An intermediate source/drain structure is introduced as a mediator between the first and second source/drain structures. This intermediate structure provides optimized electrical pathways that reduce contact resistance at critical interfaces, enabling higher integration without sacrificing reliability.
2Productivity
If the degree of integration of field effect transistors is increased, then the size of integrated circuit elements is reduced, but parasitic capacitance increases
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate, second gate, and intermediate gate) that are positioned at different heights. This vertical segmentation reduces the overlap area between gates and source/drain regions, thereby reducing parasitic capacitance while maintaining high integration density.
Solution Approach 2:
The patent transitions from a planar gate arrangement to a three-dimensional stacked gate configuration. By positioning gates at different vertical levels (first gate at first height, second gate at second height, intermediate gate at intermediate height), the design reduces parasitic capacitance through spatial separation in the vertical dimension while achieving higher integration.
3Productivity
If nanosheet stack is used with multiple nanosheets, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The nanosheet stack is segmented into multiple discrete nanosheets (first nanosheet, second nanosheet, third nanosheet) positioned at different heights. Each nanosheet can be independently controlled by corresponding gates, allowing for simplified manufacturing processes while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent utilizes vertical stacking of nanosheets in the third dimension to increase integration density without expanding the planar footprint. This three-dimensional arrangement allows multiple nanosheets to be manufactured using sequential processing steps, reducing overall manufacturing complexity compared to lateral integration.
Data Source
AI summary
An integrated circuit device may include a fin-type active structure elongated in a first horizontal direction, a nanosheet stack including nanosheets on the fin-type active structure, a gate structure extending between the nanosheets, a source/drain structure on the fin-type active structure at a position adjacent to the gate structure and facing the nanosheet stack in the first horizontal direction, a vertical separation layer including a silicon layer in contact with a silicide separation layer. The silicide separation layer may be between the source/drain structure and each of the nanosheet stack and the gate structure. The silicon separation layer may be between the silicide separation layer and each of the nanosheet stack and the gate structure. The source/drain structure may include a metal. The gate structure may include at least one sub-gate surrounding at least one nanosheet among the plurality of nanosheets on the fin-type active structure.