Nanosheet Gate Structure With Coplanar Conductors for Lower Capacitance
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces challenges in improving processing and manufacturing efficiency as the complexity of ICs increases with smaller geometry sizes.
Innovation Solution
The described method involves forming a stack of semiconductor layers over a substrate, using alternating layers of Si and SiGe with specific thicknesses and etch selectivity, and employing advanced patterning and etching processes to create nanosheet channels and dielectric features that enhance device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into multiple alternating layers of first semiconductor material and second semiconductor material, creating segmented nanosheet channels. This segmentation allows for more precise control of each layer during fabrication, reducing overall processing complexity despite smaller geometry sizes
Solution Approach 2:
The patent applies different materials with specific etch selectivity ratios to different regions of the structure. The first and second semiconductor materials have different etch rates, allowing selective removal of sacrificial layers and precise formation of nanosheet channels, thereby simplifying the patterning process
2Manufacturing precision
If alternating layers of Si and SiGe are used with specific etch selectivity, then nanosheet channels and dielectric features are enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent specifies particular thickness ranges for each layer (e.g., first semiconductor material layers 3-7 nm, second semiconductor material layers 2-5 nm) and etch selectivity ratios (e.g., SiGe to Si etch selectivity of 5:1 to 20:1). These parameter specifications enable predictable self-aligned patterning, achieving high manufacturing precision through controlled physical and chemical properties
Solution Approach 2:
The alternating layers of first and second semiconductor materials serve as both the structural building blocks and the sacrificial elements during fabrication. The differential etch rates of these materials automatically define the nanosheet channel positions and dielectric feature locations without requiring additional alignment steps, reducing manufacturing process complexity
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.