Nanosheet Gate Structure with Multilayer Spacers for Capacitance Reduction

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Solution Overview

Problem

As semiconductor devices approach integration limits, reducing effective switching capacitance (Ceff) is essential to enhance performance, but existing methods are inadequate in achieving this through structural changes.

Innovation Solution

The integrated circuit device incorporates a fin type active area with nanosheets and a gate structure that includes a main gate portion and sub-gate portions, along with multilayer insulating spacers, such as those with air spaces and different insulating materials, to reduce capacitance between the nanosheets and the gate, source, and drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the integration degree of semiconductor devices is increased, then the size of semiconductor devices is reduced, but the effective switching capacitance increases and performance deteriorates

Engineering Contradiction:

Improvesize of semiconductor deviceVSAvoidperformance of semiconductor device

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The gate structure is segmented into multiple gates (first gate, second gate, third gate, fourth gate) positioned at different locations around the nanosheet. This segmentation allows each gate to independently control the channel, reducing the effective switching capacitance while maintaining device performance. The segmented gate structure enables better electrostatic control without increasing device size.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from a planar gate structure to a three-dimensional wrap-around gate structure that surrounds the nanosheet in multiple dimensions. The gates are positioned at different heights and angular positions, creating a multi-dimensional control architecture that reduces capacitance while enhancing performance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If the gate structure is simplified, then the manufacturing process is easier, but the capacitance between gate and source/drain regions increases

Engineering Contradiction:

Improvemanufacturing process complexityVSAvoidcapacitance between gate and source/drain regions

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

Different insulating spacers are positioned at specific locations: first insulating spacers between the nanosheet and source/drain regions, and second insulating spacers between the gates and source/drain regions. This local differentiation allows precise control of capacitance in critical areas while maintaining manufacturing feasibility through standardized spacer formation processes.

Inventive Principle:

Principle #3Local quality

3Object-generated harmful factors

If insulating spacers with air spaces are used, then the capacitance between gate and source/drain regions is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:

Improvecapacitance between gate and source/drain regionsVSAvoidprecision of insulating spacer formation

Core Design Contradiction:

Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The insulating spacers are formed as preliminary structures before the gates are positioned. The first insulating spacers are formed between the nanosheet and source/drain regions, and the second insulating spacers are formed between the gates and source/drain regions. This preliminary formation allows precise control of spacer dimensions and positions, reducing manufacturing precision requirements for subsequent steps.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10096688B2Integrated circuit device and method of manufacturing the same

Publication Date: 2018.10.09 SAMSUNG ELECTRONICS CO LTD

AI summary

An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.