Nanosheet Gate Oxide Layout for Mixed-Voltage Transistor Scaling
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Solution Overview
Problem
The production of nanosheet FET devices faces challenges in achieving sufficient spacing between nanosheets, which affects the deposition of high-k metal gates and limits device scaling, especially at production nodes below 5 nm, and requires thicker gate dielectrics for higher voltage operations while maintaining small spacing for capacitance benefits.
Innovation Solution
The process involves forming nanosheet stacks with alternating sacrificial and channel layers, where the second stack has sacrificial layers with increased height and fewer channel layers, allowing for the deposition of a thicker gate dielectric material by removing sacrificial layers to create voids that accommodate the dielectric, enabling both small and thick gate dielectric transistor structures on the same chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet stacks are scaled to smaller dimensions to increase effective channel width per footprint area, then device integration density is improved, but spacing between nanosheets becomes insufficient for proper gate dielectric deposition
Solution Approach 1:
The patent transitions from planar spacing to vertical stacking, arranging nanosheets in multiple layers along the vertical dimension. This allows sufficient effective channel width to be achieved through stacked configurations rather than lateral expansion, maintaining adequate spacing between individual nanosheets while increasing integration density in the vertical direction.
Solution Approach 2:
The patent divides the gate structure into multiple discrete nanosheet segments stacked vertically, with each nanosheet maintaining its own spacing. This segmentation allows each nanosheet to be properly formed with adequate dielectric spacing while the collective stack provides the required effective channel width for high-density integration.
2Reliability
If thicker gate dielectrics are deposited to accommodate higher voltage operations, then voltage handling capability is improved, but spacing between nanosheets must be increased which reduces integration density
Solution Approach 1:
The patent enables thicker gate dielectric deposition by utilizing the vertical dimension of the stacked nanosheet configuration. The increased vertical spacing in the stack allows sufficient room for thicker dielectric layers to be deposited between nanosheets, accommodating higher voltage operations while maintaining high integration density through the stacked architecture.
3Productivity
If smaller spacing between nanosheets is maintained for capacitance benefits, then device performance is improved, but gate dielectric deposition becomes difficult especially for thicker dielectrics
Solution Approach 1:
The stacked nanosheet configuration provides enhanced vertical access and spacing that facilitates gate dielectric deposition. The vertical stacking geometry allows deposition processes to effectively reach and coat the gate dielectric between nanosheets, even when horizontal spacing is minimized for performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes spacing for gate dielectric deposition, accommodating both low-voltage logic and high-voltage input/output devices, enhancing device scaling and performance by allowing for the integration of both small and extended gate dielectric transistor structures on a single semiconductor substrate.
Implementation Method 1
A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures
Implementation Method 2
A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures
Data Source
AI summary
A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.