Nanosheet Gate Structure to Suppress Parasitic Transistors
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Solution Overview
Problem
As semiconductor devices shrink, the integration of electric field-effect transistors leads to degraded electrical characteristics due to unwanted parasitic transistors, necessitating a new structure to suppress their formation.
Innovation Solution
The proposed IC device structure includes a fin-type active area with nanosheet stack structures and a gate line configuration that prevents the formation of unwanted parasitic transistors by using a bottom insulation structure and gate dielectric layer, ensuring optimal electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the integration degree of semiconductor devices is increased to reduce device size, then device miniaturization is achieved, but electrical characteristics are degraded due to unwanted parasitic transistors
Solution Approach 1:
The gate line is segmented into multiple gate portions (first gate portion, second gate portion, third gate portion) that are spatially separated and independently positioned relative to different nanosheets. This segmentation allows selective control over each nanosheet while preventing the formation of unwanted parasitic transistors in inter-nanosheet regions, thus maintaining electrical characteristics during device miniaturization.
Solution Approach 2:
An insulation structure is introduced as an intermediary element between the fin-type active area and the nanosheet stack structure. This insulation structure fills the separation space and prevents electrical interaction that would otherwise create parasitic transistors, thereby preserving electrical characteristics while enabling higher integration density.
2Productivity
If multiple nanosheets are stacked on the same layout area to increase integration degree, then device density is improved, but formation of unwanted parasitic transistors occurs
Solution Approach 1:
Different regions of the device are assigned different functional qualities: the insulation structure is placed specifically in separation spaces between nanosheets to prevent parasitic transistor formation, while the gate line portions are positioned to provide control only where needed. This local differentiation allows high device density without generating harmful parasitic effects.
Solution Approach 2:
The harmful electrical interaction that leads to parasitic transistor formation is extracted or removed from the system by introducing the insulation structure in separation spaces. This eliminates the unwanted parasitic transistors while preserving the beneficial high-density nanosheet stacking configuration.
3Area of stationary object
If nanosheet stack structure is disposed close to fin-type active area to save space, then area utilization is improved, but parasitic capacitance increases
Solution Approach 1:
The insulation structure serves as a mediator between the fin-type active area and the nanosheet stack structure, filling the separation space to prevent direct electrical interaction. This eliminates parasitic capacitance formation while allowing the components to be positioned close together for optimal area utilization.
4Device complexity
If gate line extends continuously across all nanosheets to provide uniform control, then gate control is simplified, but unwanted parasitic transistors are formed in separation spaces
Solution Approach 1:
The gate line is divided into discrete gate portions (first, second, and third gate portions) that are separated by insulation structures. This segmentation prevents continuous electrical connection across separation spaces, eliminating parasitic transistor formation while maintaining relatively simple gate control through the segmented structure.
Data Source
AI summary
An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.