Nanosheet Transistor Metal Gate Passivation Against Oxidation
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Solution Overview
Problem
In the fabrication of gate all around transistors, there are challenges in forming gate metals for N-type and P-type transistors, particularly in preventing oxidation of the thin metal gate layers which affects the work function, threshold voltage, and overall resistance.
Innovation Solution
The solution involves forming a passivation layer in-situ with the thin metal gate layer, specifically for the P-type transistors, to prevent oxidation and ensure high work functions, low threshold voltages, and low overall resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a thin metal gate layer is formed for P-type transistors, then the transistor can achieve low threshold voltage and high computing power, but the thin metal gate layer is prone to oxidation which degrades electrical characteristics
Solution Approach 1:
A titanium nitride (TiN) barrier layer is introduced as an intermediary between the metal gate layer and the surrounding environment. This TiN layer serves as a protective mediator that prevents oxidation of the thin metal gate layer while allowing the transistor to maintain its low threshold voltage and high computing power characteristics.
Solution Approach 2:
The patent creates an inert protective environment around the thin metal gate layer by depositing titanium nitride, which forms an oxidation-resistant barrier. This inert layer shields the reactive metal gate material from oxygen exposure, preventing degradation of electrical characteristics while preserving the low threshold voltage needed for high computing power.
2Reliability
If different gate metals are used for N-type and P-type transistors, then optimal electrical characteristics can be achieved for each transistor type, but the fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: first forming the metal gate layer for both N-type and P-type transistors, then selectively removing it from N-type regions, and finally depositing TiN only in P-type regions. This segmentation allows different gate metal configurations for different transistor types while managing process complexity through systematic, separated steps.
Solution Approach 2:
The patent applies local quality by implementing different gate structures in different regions: P-type transistors receive the TiN barrier layer while N-type transistors do not. This localized differentiation allows optimal electrical characteristics for each transistor type to be achieved through region-specific processing rather than uniform treatment across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance of integrated circuits with higher wafer yields and reduced scrap rates, as the passivation layer effectively prevents oxidation and maintains optimal electrical characteristics.
Implementation Method 1
depositing a passivation layer on the thin metal gate layer in-situ with deposition of the thin metal gate layer
Data Source
AI summary
A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a first metal gate layer for the P-type transistors and a second metal gate layer for the N-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistors.