Nanosheet Metal Gate Passivation for Oxidation-Stable P-Type GAA Transistors

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Solution Overview

Problem

In semiconductor fabrication, forming gate metals for N-type and P-type transistors in gate all around transistors is challenging due to material and process differences, leading to issues such as oxidation of thin metal gate layers, which affects work functions and threshold voltages, resulting in higher resistance and lower wafer yields.

Innovation Solution

The formation of a passivation layer in-situ with the thin metal gate layer during deposition prevents oxidation, ensuring high work functions and low threshold voltages for P-type transistors, while maintaining low resistance, by controlling the environment to prevent oxygen and other element diffusion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a thin metal gate layer is formed for P-type transistors, then the threshold voltage and work function are improved, but oxidation occurs leading to higher resistance and lower yield

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidoxidation resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent uses a composite structure consisting of a thin metal gate layer (e.g., tungsten, titanium nitride) combined with a dielectric passivation layer (e.g., silicon oxide, silicon nitride). This composite structure allows the metal layer to provide the desired work function and threshold voltage characteristics while the dielectric layer protects against oxidation, thereby resolving the contradiction between achieving precise threshold voltage control and maintaining oxidation resistance.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent employs an inert or oxygen-free environment during the formation and processing of the thin metal gate layer. By controlling the atmospheric environment to be oxygen-depleted or filled with inert gases, the metal gate layer is protected from oxidation during fabrication, thus maintaining its electrical properties and preventing the formation of high-resistance oxide layers.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Speed

If the metal gate layer is made thinner to improve transistor performance, then switching speed increases, but oxidation becomes more severe

Engineering Contradiction:
Improvetransistor switching speedVSAvoidoxidation susceptibility
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent applies a thin dielectric passivation film over the thin metal gate layer to provide protection against oxidation. This thin film acts as a protective shell that prevents oxygen from reaching and oxidizing the metal gate material, thereby allowing the use of thinner metal layers for improved switching speed without suffering from oxidation-related degradation.

Inventive Principle:
Principle #30Flexible shells and thin films

Solution Approach 2:

The patent performs preliminary protective actions by depositing the dielectric passivation layer immediately after forming the thin metal gate layer, while the metal layer is still in a reactive state. This preliminary protection prevents oxidation from occurring during subsequent processing steps, allowing the thin metal gate to maintain its intended electrical characteristics.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If different materials are used for N-type and P-type gate electrodes, then transistor performance is optimized, but process complexity increases

Engineering Contradiction:
Improvetransistor type optimizationVSAvoidfabrication process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by using different metal gate materials for N-type and P-type transistors based on their specific electrical requirements. N-type transistors may use metals with lower work functions while P-type transistors use metals with higher work functions, allowing each transistor type to be optimized for its specific function. The dielectric passivation layer is applied selectively or uniformly to protect the appropriate metal gates.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dielectric passivation layer serves multiple functions: it protects metal gate layers from oxidation, provides electrical isolation, and can be used as part of the gate structure in both N-type and P-type transistors. This multi-functional approach allows the same protective layer structure to be used across different transistor types, reducing overall process complexity despite using different metal materials.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in improved performance of integrated circuits with higher yields, lower scrapped wafers, and better functioning transistors by maintaining high work functions and low resistance, specifically for P-type transistors.

Implementation Method 1

depositing a passivation layer on the thin metal gate layer in-situ with deposition of the thin metal gate layer. This prevents oxidation of the thin metal gate layer

Methodology Applied
Scientific EffectOxidation prevention: Diffusion Barrier

Implementation Method 2

depositing a passivation layer on the thin metal gate layer in-situ with deposition of the thin metal gate layer

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS20240379367A1Integrated circuit with nanosheet transistors with metal gate passivation
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379367A1 patent drawing
  • US20240379367A1 patent drawing
  • US20240379367A1 patent drawing

AI summary

A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a metal gate layer for the P-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistor.