Nanosheet Gate Patterning for Threshold Voltage Control
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Solution Overview
Problem
The challenge in fabricating gate-all-around (GAA) transistors with multiple threshold voltages (Vts) is the difficulty in patterning metal gate layers due to the narrow space between adjacent channels and small gate pitch, leading to metal gate material loss and voltage drift during wet over-etching, which complicates device manufacturing and affects device performance.
Innovation Solution
An n-type metal gate patterning-first process is employed, avoiding lateral removal of the n-type metal gate in the NFET region through wet etching, thereby minimizing metal gate material loss and eliminating voltage variation, and allowing for more precise control over cell height and gate pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet over-etching is applied to remove metal gate material in one region, then complete removal is achieved, but metal gate material loss occurs in neighboring regions causing voltage drift
Solution Approach 1:
The patent divides the gate patterning process into multiple sequential steps: first forming a sacrificial layer and patterned mask, then selectively removing metal gate material in regions where the mask is absent, while preserving it where the mask remains. This segmentation allows precise spatial control over metal gate removal, preventing lateral etching damage to adjacent regions.
Solution Approach 2:
The patent applies preliminary protective actions by depositing a sacrificial layer and patterned mask before performing the wet over-etching process. These preliminary structures serve as protective barriers that prevent unwanted lateral removal of metal gate material during etching, while still allowing complete removal in targeted regions.
2Adaptability or versatility
If metal gate layers are patterned to enable multiple threshold voltages, then device functionality is improved, but processing limitations occur due to narrow space between adjacent GAA channels
Solution Approach 1:
The patent transitions from planar 2D gate patterning to 3D gate-all-around structures by forming metal gate material that completely surrounds the channel in three dimensions. This dimensional change enables multiple threshold voltage control through selective removal of gate material in different spatial regions, while the vertical stacking of nanosheets provides additional degrees of freedom for patterning.
Solution Approach 2:
The patent introduces intermediary structures including sacrificial layers and patterned masks that mediate the complex gate patterning process. These intermediaries enable precise control over metal gate formation in narrow spaces between adjacent channels by providing temporary protective and guiding structures during the patterning sequence.
3Productivity
If gate pitch and cell height are scaled down, then production efficiency increases, but processing window tightens causing patterning challenges
Solution Approach 1:
The patent employs multiple parameter changes including varying etchant selectivities, adjusting deposition thicknesses, and modifying pattern dimensions at different stages. These parameter adjustments enable precise control over gate patterning even as overall device dimensions are scaled down, maintaining manufacturing precision while improving productivity through aggressive scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of threshold voltage control and uniformity in NFETs, reduces metal gate loss, and expands the patterning window for GAA transistors, facilitating more aggressive scaling in both cell height and gate pitch directions.
Implementation Method 1
selectively removing the cap layer and the n-type work function metal layer in the p-type device region
Data Source
AI summary
A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.